2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "keyboard.dtsi"
14 /include/ "serial.dtsi"
16 /include/ "tsc_timer.dtsi"
19 model = "Intel Bayley Bay";
20 compatible = "intel,bayleybay", "intel,baytrail";
32 stdout-path = "/serial";
41 compatible = "intel,baytrail-cpu";
48 compatible = "intel,baytrail-cpu";
55 compatible = "intel,baytrail-cpu";
62 compatible = "intel,baytrail-cpu";
69 compatible = "intel,ich6-gpio";
76 compatible = "intel,ich6-gpio";
83 compatible = "intel,ich6-gpio";
90 compatible = "intel,ich6-gpio";
97 compatible = "intel,ich6-gpio";
104 compatible = "intel,ich6-gpio";
111 compatible = "pci-x86";
112 #address-cells = <3>;
115 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
116 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
117 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
120 reg = <0x0000f800 0 0 0 0>;
121 compatible = "intel,pch9";
124 compatible = "intel,irq-router";
125 intel,pirq-config = "ibase";
126 intel,ibase-offset = <0x50>;
127 intel,pirq-link = <8 8>;
128 intel,pirq-mask = <0xdee0>;
129 intel,pirq-routing = <
130 /* BayTrail PCI devices */
131 PCI_BDF(0, 2, 0) INTA PIRQA
132 PCI_BDF(0, 3, 0) INTA PIRQA
133 PCI_BDF(0, 16, 0) INTA PIRQA
134 PCI_BDF(0, 17, 0) INTA PIRQA
135 PCI_BDF(0, 18, 0) INTA PIRQA
136 PCI_BDF(0, 19, 0) INTA PIRQA
137 PCI_BDF(0, 20, 0) INTA PIRQA
138 PCI_BDF(0, 21, 0) INTA PIRQA
139 PCI_BDF(0, 22, 0) INTA PIRQA
140 PCI_BDF(0, 23, 0) INTA PIRQA
141 PCI_BDF(0, 24, 0) INTA PIRQA
142 PCI_BDF(0, 24, 1) INTC PIRQC
143 PCI_BDF(0, 24, 2) INTD PIRQD
144 PCI_BDF(0, 24, 3) INTB PIRQB
145 PCI_BDF(0, 24, 4) INTA PIRQA
146 PCI_BDF(0, 24, 5) INTC PIRQC
147 PCI_BDF(0, 24, 6) INTD PIRQD
148 PCI_BDF(0, 24, 7) INTB PIRQB
149 PCI_BDF(0, 26, 0) INTA PIRQA
150 PCI_BDF(0, 27, 0) INTA PIRQA
151 PCI_BDF(0, 28, 0) INTA PIRQA
152 PCI_BDF(0, 28, 1) INTB PIRQB
153 PCI_BDF(0, 28, 2) INTC PIRQC
154 PCI_BDF(0, 28, 3) INTD PIRQD
155 PCI_BDF(0, 29, 0) INTA PIRQA
156 PCI_BDF(0, 30, 0) INTA PIRQA
157 PCI_BDF(0, 30, 1) INTD PIRQD
158 PCI_BDF(0, 30, 2) INTB PIRQB
159 PCI_BDF(0, 30, 3) INTC PIRQC
160 PCI_BDF(0, 30, 4) INTD PIRQD
161 PCI_BDF(0, 30, 5) INTB PIRQB
162 PCI_BDF(0, 31, 3) INTB PIRQB
165 * PCIe root ports downstream
168 PCI_BDF(1, 0, 0) INTA PIRQA
169 PCI_BDF(1, 0, 0) INTB PIRQB
170 PCI_BDF(1, 0, 0) INTC PIRQC
171 PCI_BDF(1, 0, 0) INTD PIRQD
172 PCI_BDF(2, 0, 0) INTA PIRQB
173 PCI_BDF(2, 0, 0) INTB PIRQC
174 PCI_BDF(2, 0, 0) INTC PIRQD
175 PCI_BDF(2, 0, 0) INTD PIRQA
176 PCI_BDF(3, 0, 0) INTA PIRQC
177 PCI_BDF(3, 0, 0) INTB PIRQD
178 PCI_BDF(3, 0, 0) INTC PIRQA
179 PCI_BDF(3, 0, 0) INTD PIRQB
180 PCI_BDF(4, 0, 0) INTA PIRQD
181 PCI_BDF(4, 0, 0) INTB PIRQA
182 PCI_BDF(4, 0, 0) INTC PIRQB
183 PCI_BDF(4, 0, 0) INTD PIRQC
188 #address-cells = <1>;
190 compatible = "intel,ich-spi";
192 #address-cells = <1>;
195 compatible = "winbond,w25q64dw",
197 memory-map = <0xff800000 0x00800000>;
199 label = "rw-mrc-cache";
200 reg = <0x006e0000 0x00010000>;
208 compatible = "intel,baytrail-fsp";
209 fsp,mrc-init-tseg-size = <0>;
210 fsp,mrc-init-mmio-size = <0x800>;
211 fsp,mrc-init-spd-addr1 = <0xa0>;
212 fsp,mrc-init-spd-addr2 = <0xa2>;
213 fsp,emmc-boot-mode = <2>;
221 fsp,lpss-sio-enable-pci-mode;
233 fsp,igd-dvmt50-pre-alloc = <2>;
234 fsp,aperture-size = <2>;
236 fsp,serial-debug-port-address = <0x3f8>;
237 fsp,serial-debug-port-type = <1>;
238 fsp,scc-enable-pci-mode;
239 fsp,os-selection = <4>;
240 fsp,emmc45-ddr50-enabled;
241 fsp,emmc45-retune-timer-value = <8>;
247 #include "microcode/m0230671117.dtsi"
250 #include "microcode/m0130673322.dtsi"
253 #include "microcode/m0130679901.dtsi"