2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "keyboard.dtsi"
14 /include/ "serial.dtsi"
16 /include/ "tsc_timer.dtsi"
19 model = "Intel Bayley Bay";
20 compatible = "intel,bayleybay", "intel,baytrail";
32 stdout-path = "/serial";
41 compatible = "intel,baytrail-cpu";
48 compatible = "intel,baytrail-cpu";
55 compatible = "intel,baytrail-cpu";
62 compatible = "intel,baytrail-cpu";
69 compatible = "intel,x86-pinctrl";
73 * As of today, the latest version FSP (gold4) for BayTrail
74 * misses the PAD configuration of the SD controller's Card
75 * Detect signal. The default PAD value for the CD pin sets
76 * the pin to work in GPIO mode, which causes card detect
77 * status cannot be reflected by the Present State register
78 * in the SD controller (bit 16 & bit 18 are always zero).
80 * Configure this pin to function 1 (SD controller).
89 compatible = "pci-x86";
93 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
94 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
95 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
98 reg = <0x0000f800 0 0 0 0>;
99 compatible = "intel,pch9";
100 #address-cells = <1>;
104 compatible = "intel,irq-router";
105 intel,pirq-config = "ibase";
106 intel,ibase-offset = <0x50>;
107 intel,actl-addr = <0>;
108 intel,pirq-link = <8 8>;
109 intel,pirq-mask = <0xdee0>;
110 intel,pirq-routing = <
111 /* BayTrail PCI devices */
112 PCI_BDF(0, 2, 0) INTA PIRQA
113 PCI_BDF(0, 3, 0) INTA PIRQA
114 PCI_BDF(0, 16, 0) INTA PIRQA
115 PCI_BDF(0, 17, 0) INTA PIRQA
116 PCI_BDF(0, 18, 0) INTA PIRQA
117 PCI_BDF(0, 19, 0) INTA PIRQA
118 PCI_BDF(0, 20, 0) INTA PIRQA
119 PCI_BDF(0, 21, 0) INTA PIRQA
120 PCI_BDF(0, 22, 0) INTA PIRQA
121 PCI_BDF(0, 23, 0) INTA PIRQA
122 PCI_BDF(0, 24, 0) INTA PIRQA
123 PCI_BDF(0, 24, 1) INTC PIRQC
124 PCI_BDF(0, 24, 2) INTD PIRQD
125 PCI_BDF(0, 24, 3) INTB PIRQB
126 PCI_BDF(0, 24, 4) INTA PIRQA
127 PCI_BDF(0, 24, 5) INTC PIRQC
128 PCI_BDF(0, 24, 6) INTD PIRQD
129 PCI_BDF(0, 24, 7) INTB PIRQB
130 PCI_BDF(0, 26, 0) INTA PIRQA
131 PCI_BDF(0, 27, 0) INTA PIRQA
132 PCI_BDF(0, 28, 0) INTA PIRQA
133 PCI_BDF(0, 28, 1) INTB PIRQB
134 PCI_BDF(0, 28, 2) INTC PIRQC
135 PCI_BDF(0, 28, 3) INTD PIRQD
136 PCI_BDF(0, 29, 0) INTA PIRQA
137 PCI_BDF(0, 30, 0) INTA PIRQA
138 PCI_BDF(0, 30, 1) INTD PIRQD
139 PCI_BDF(0, 30, 2) INTB PIRQB
140 PCI_BDF(0, 30, 3) INTC PIRQC
141 PCI_BDF(0, 30, 4) INTD PIRQD
142 PCI_BDF(0, 30, 5) INTB PIRQB
143 PCI_BDF(0, 31, 3) INTB PIRQB
146 * PCIe root ports downstream
149 PCI_BDF(1, 0, 0) INTA PIRQA
150 PCI_BDF(1, 0, 0) INTB PIRQB
151 PCI_BDF(1, 0, 0) INTC PIRQC
152 PCI_BDF(1, 0, 0) INTD PIRQD
153 PCI_BDF(2, 0, 0) INTA PIRQB
154 PCI_BDF(2, 0, 0) INTB PIRQC
155 PCI_BDF(2, 0, 0) INTC PIRQD
156 PCI_BDF(2, 0, 0) INTD PIRQA
157 PCI_BDF(3, 0, 0) INTA PIRQC
158 PCI_BDF(3, 0, 0) INTB PIRQD
159 PCI_BDF(3, 0, 0) INTC PIRQA
160 PCI_BDF(3, 0, 0) INTD PIRQB
161 PCI_BDF(4, 0, 0) INTA PIRQD
162 PCI_BDF(4, 0, 0) INTB PIRQA
163 PCI_BDF(4, 0, 0) INTC PIRQB
164 PCI_BDF(4, 0, 0) INTD PIRQC
169 #address-cells = <1>;
171 compatible = "intel,ich9-spi";
173 #address-cells = <1>;
176 compatible = "winbond,w25q64dw",
178 memory-map = <0xff800000 0x00800000>;
180 label = "rw-mrc-cache";
181 reg = <0x006e0000 0x00010000>;
187 compatible = "intel,ich6-gpio";
194 compatible = "intel,ich6-gpio";
201 compatible = "intel,ich6-gpio";
208 compatible = "intel,ich6-gpio";
215 compatible = "intel,ich6-gpio";
222 compatible = "intel,ich6-gpio";
231 compatible = "intel,baytrail-fsp";
232 fsp,mrc-init-tseg-size = <0>;
233 fsp,mrc-init-mmio-size = <0x800>;
234 fsp,mrc-init-spd-addr1 = <0xa0>;
235 fsp,mrc-init-spd-addr2 = <0xa2>;
236 fsp,emmc-boot-mode = <1>;
244 fsp,lpss-sio-enable-pci-mode;
256 fsp,igd-dvmt50-pre-alloc = <2>;
257 fsp,aperture-size = <2>;
259 fsp,serial-debug-port-address = <0x3f8>;
260 fsp,serial-debug-port-type = <1>;
261 fsp,scc-enable-pci-mode;
262 fsp,os-selection = <4>;
263 fsp,emmc45-ddr50-enabled;
264 fsp,emmc45-retune-timer-value = <8>;
270 #include "microcode/m0230671117.dtsi"
273 #include "microcode/m0130673325.dtsi"
276 #include "microcode/m0130679907.dtsi"