2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/gpio/x86-gpio.h>
10 #include <dt-bindings/interrupt-router/intel-irq.h>
12 /include/ "skeleton.dtsi"
13 /include/ "keyboard.dtsi"
14 /include/ "serial.dtsi"
16 /include/ "tsc_timer.dtsi"
17 /include/ "coreboot_fb.dtsi"
20 model = "Intel Bayley Bay";
21 compatible = "intel,bayleybay", "intel,baytrail";
33 stdout-path = "/serial";
42 compatible = "intel,baytrail-cpu";
49 compatible = "intel,baytrail-cpu";
56 compatible = "intel,baytrail-cpu";
63 compatible = "intel,baytrail-cpu";
70 compatible = "intel,x86-pinctrl";
74 * As of today, the latest version FSP (gold4) for BayTrail
75 * misses the PAD configuration of the SD controller's Card
76 * Detect signal. The default PAD value for the CD pin sets
77 * the pin to work in GPIO mode, which causes card detect
78 * status cannot be reflected by the Present State register
79 * in the SD controller (bit 16 & bit 18 are always zero).
81 * Configure this pin to function 1 (SD controller).
90 compatible = "pci-x86";
94 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
95 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
96 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
99 reg = <0x0000f800 0 0 0 0>;
100 compatible = "intel,pch9";
101 #address-cells = <1>;
105 compatible = "intel,irq-router";
106 intel,pirq-config = "ibase";
107 intel,ibase-offset = <0x50>;
108 intel,actl-addr = <0>;
109 intel,pirq-link = <8 8>;
110 intel,pirq-mask = <0xdee0>;
111 intel,pirq-routing = <
112 /* BayTrail PCI devices */
113 PCI_BDF(0, 2, 0) INTA PIRQA
114 PCI_BDF(0, 3, 0) INTA PIRQA
115 PCI_BDF(0, 16, 0) INTA PIRQA
116 PCI_BDF(0, 17, 0) INTA PIRQA
117 PCI_BDF(0, 18, 0) INTA PIRQA
118 PCI_BDF(0, 19, 0) INTA PIRQA
119 PCI_BDF(0, 20, 0) INTA PIRQA
120 PCI_BDF(0, 21, 0) INTA PIRQA
121 PCI_BDF(0, 22, 0) INTA PIRQA
122 PCI_BDF(0, 23, 0) INTA PIRQA
123 PCI_BDF(0, 24, 0) INTA PIRQA
124 PCI_BDF(0, 24, 1) INTC PIRQC
125 PCI_BDF(0, 24, 2) INTD PIRQD
126 PCI_BDF(0, 24, 3) INTB PIRQB
127 PCI_BDF(0, 24, 4) INTA PIRQA
128 PCI_BDF(0, 24, 5) INTC PIRQC
129 PCI_BDF(0, 24, 6) INTD PIRQD
130 PCI_BDF(0, 24, 7) INTB PIRQB
131 PCI_BDF(0, 26, 0) INTA PIRQA
132 PCI_BDF(0, 27, 0) INTA PIRQA
133 PCI_BDF(0, 28, 0) INTA PIRQA
134 PCI_BDF(0, 28, 1) INTB PIRQB
135 PCI_BDF(0, 28, 2) INTC PIRQC
136 PCI_BDF(0, 28, 3) INTD PIRQD
137 PCI_BDF(0, 29, 0) INTA PIRQA
138 PCI_BDF(0, 30, 0) INTA PIRQA
139 PCI_BDF(0, 30, 1) INTD PIRQD
140 PCI_BDF(0, 30, 2) INTB PIRQB
141 PCI_BDF(0, 30, 3) INTC PIRQC
142 PCI_BDF(0, 30, 4) INTD PIRQD
143 PCI_BDF(0, 30, 5) INTB PIRQB
144 PCI_BDF(0, 31, 3) INTB PIRQB
147 * PCIe root ports downstream
150 PCI_BDF(1, 0, 0) INTA PIRQA
151 PCI_BDF(1, 0, 0) INTB PIRQB
152 PCI_BDF(1, 0, 0) INTC PIRQC
153 PCI_BDF(1, 0, 0) INTD PIRQD
154 PCI_BDF(2, 0, 0) INTA PIRQB
155 PCI_BDF(2, 0, 0) INTB PIRQC
156 PCI_BDF(2, 0, 0) INTC PIRQD
157 PCI_BDF(2, 0, 0) INTD PIRQA
158 PCI_BDF(3, 0, 0) INTA PIRQC
159 PCI_BDF(3, 0, 0) INTB PIRQD
160 PCI_BDF(3, 0, 0) INTC PIRQA
161 PCI_BDF(3, 0, 0) INTD PIRQB
162 PCI_BDF(4, 0, 0) INTA PIRQD
163 PCI_BDF(4, 0, 0) INTB PIRQA
164 PCI_BDF(4, 0, 0) INTC PIRQB
165 PCI_BDF(4, 0, 0) INTD PIRQC
170 #address-cells = <1>;
172 compatible = "intel,ich9-spi";
174 #address-cells = <1>;
177 compatible = "winbond,w25q64dw",
179 memory-map = <0xff800000 0x00800000>;
181 label = "rw-mrc-cache";
182 reg = <0x006e0000 0x00010000>;
188 compatible = "intel,ich6-gpio";
195 compatible = "intel,ich6-gpio";
202 compatible = "intel,ich6-gpio";
209 compatible = "intel,ich6-gpio";
216 compatible = "intel,ich6-gpio";
223 compatible = "intel,ich6-gpio";
232 compatible = "intel,baytrail-fsp";
233 fsp,mrc-init-tseg-size = <0>;
234 fsp,mrc-init-mmio-size = <0x800>;
235 fsp,mrc-init-spd-addr1 = <0xa0>;
236 fsp,mrc-init-spd-addr2 = <0xa2>;
237 fsp,emmc-boot-mode = <1>;
245 fsp,lpss-sio-enable-pci-mode;
257 fsp,igd-dvmt50-pre-alloc = <2>;
258 fsp,aperture-size = <2>;
260 fsp,serial-debug-port-address = <0x3f8>;
261 fsp,serial-debug-port-type = <1>;
262 fsp,scc-enable-pci-mode;
263 fsp,os-selection = <4>;
264 fsp,emmc45-ddr50-enabled;
265 fsp,emmc45-retune-timer-value = <8>;
271 #include "microcode/m0230671117.dtsi"
274 #include "microcode/m0130673325.dtsi"
277 #include "microcode/m0130679907.dtsi"