2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-baytrail/fsp/fsp_configs.h>
10 #include <dt-bindings/gpio/x86-gpio.h>
11 #include <dt-bindings/interrupt-router/intel-irq.h>
13 /include/ "skeleton.dtsi"
14 /include/ "keyboard.dtsi"
15 /include/ "serial.dtsi"
17 /include/ "tsc_timer.dtsi"
18 /include/ "coreboot_fb.dtsi"
21 model = "Intel Bayley Bay";
22 compatible = "intel,bayleybay", "intel,baytrail";
34 stdout-path = "/serial";
43 compatible = "intel,baytrail-cpu";
50 compatible = "intel,baytrail-cpu";
57 compatible = "intel,baytrail-cpu";
64 compatible = "intel,baytrail-cpu";
71 compatible = "intel,x86-pinctrl";
75 * As of today, the latest version FSP (gold4) for BayTrail
76 * misses the PAD configuration of the SD controller's Card
77 * Detect signal. The default PAD value for the CD pin sets
78 * the pin to work in GPIO mode, which causes card detect
79 * status cannot be reflected by the Present State register
80 * in the SD controller (bit 16 & bit 18 are always zero).
82 * Configure this pin to function 1 (SD controller).
91 compatible = "pci-x86";
95 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
96 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
97 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
100 reg = <0x0000f800 0 0 0 0>;
101 compatible = "intel,pch9";
102 #address-cells = <1>;
106 compatible = "intel,irq-router";
107 intel,pirq-config = "ibase";
108 intel,ibase-offset = <0x50>;
109 intel,actl-addr = <0>;
110 intel,pirq-link = <8 8>;
111 intel,pirq-mask = <0xdee0>;
112 intel,pirq-routing = <
113 /* BayTrail PCI devices */
114 PCI_BDF(0, 2, 0) INTA PIRQA
115 PCI_BDF(0, 3, 0) INTA PIRQA
116 PCI_BDF(0, 16, 0) INTA PIRQA
117 PCI_BDF(0, 17, 0) INTA PIRQA
118 PCI_BDF(0, 18, 0) INTA PIRQA
119 PCI_BDF(0, 19, 0) INTA PIRQA
120 PCI_BDF(0, 20, 0) INTA PIRQA
121 PCI_BDF(0, 21, 0) INTA PIRQA
122 PCI_BDF(0, 22, 0) INTA PIRQA
123 PCI_BDF(0, 23, 0) INTA PIRQA
124 PCI_BDF(0, 24, 0) INTA PIRQA
125 PCI_BDF(0, 24, 1) INTC PIRQC
126 PCI_BDF(0, 24, 2) INTD PIRQD
127 PCI_BDF(0, 24, 3) INTB PIRQB
128 PCI_BDF(0, 24, 4) INTA PIRQA
129 PCI_BDF(0, 24, 5) INTC PIRQC
130 PCI_BDF(0, 24, 6) INTD PIRQD
131 PCI_BDF(0, 24, 7) INTB PIRQB
132 PCI_BDF(0, 26, 0) INTA PIRQA
133 PCI_BDF(0, 27, 0) INTA PIRQA
134 PCI_BDF(0, 28, 0) INTA PIRQA
135 PCI_BDF(0, 28, 1) INTB PIRQB
136 PCI_BDF(0, 28, 2) INTC PIRQC
137 PCI_BDF(0, 28, 3) INTD PIRQD
138 PCI_BDF(0, 29, 0) INTA PIRQA
139 PCI_BDF(0, 30, 0) INTA PIRQA
140 PCI_BDF(0, 30, 1) INTD PIRQD
141 PCI_BDF(0, 30, 2) INTB PIRQB
142 PCI_BDF(0, 30, 3) INTC PIRQC
143 PCI_BDF(0, 30, 4) INTD PIRQD
144 PCI_BDF(0, 30, 5) INTB PIRQB
145 PCI_BDF(0, 31, 3) INTB PIRQB
148 * PCIe root ports downstream
151 PCI_BDF(1, 0, 0) INTA PIRQA
152 PCI_BDF(1, 0, 0) INTB PIRQB
153 PCI_BDF(1, 0, 0) INTC PIRQC
154 PCI_BDF(1, 0, 0) INTD PIRQD
155 PCI_BDF(2, 0, 0) INTA PIRQB
156 PCI_BDF(2, 0, 0) INTB PIRQC
157 PCI_BDF(2, 0, 0) INTC PIRQD
158 PCI_BDF(2, 0, 0) INTD PIRQA
159 PCI_BDF(3, 0, 0) INTA PIRQC
160 PCI_BDF(3, 0, 0) INTB PIRQD
161 PCI_BDF(3, 0, 0) INTC PIRQA
162 PCI_BDF(3, 0, 0) INTD PIRQB
163 PCI_BDF(4, 0, 0) INTA PIRQD
164 PCI_BDF(4, 0, 0) INTB PIRQA
165 PCI_BDF(4, 0, 0) INTC PIRQB
166 PCI_BDF(4, 0, 0) INTD PIRQC
171 #address-cells = <1>;
173 compatible = "intel,ich9-spi";
175 #address-cells = <1>;
178 compatible = "winbond,w25q64dw",
180 memory-map = <0xff800000 0x00800000>;
182 label = "rw-mrc-cache";
183 reg = <0x006e0000 0x00010000>;
189 compatible = "intel,ich6-gpio";
197 compatible = "intel,ich6-gpio";
205 compatible = "intel,ich6-gpio";
213 compatible = "intel,ich6-gpio";
221 compatible = "intel,ich6-gpio";
229 compatible = "intel,ich6-gpio";
239 compatible = "intel,baytrail-fsp";
240 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
241 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
242 fsp,mrc-init-spd-addr1 = <0xa0>;
243 fsp,mrc-init-spd-addr2 = <0xa2>;
244 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
250 fsp,sata-mode = <SATA_MODE_AHCI>;
251 fsp,lpe-mode = <LPE_MODE_PCI>;
252 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
264 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
265 fsp,aperture-size = <APERTURE_SIZE_256MB>;
266 fsp,gtt-size = <GTT_SIZE_2MB>;
267 fsp,scc-mode = <SCC_MODE_PCI>;
268 fsp,os-selection = <OS_SELECTION_LINUX>;
269 fsp,emmc45-ddr50-enabled;
270 fsp,emmc45-retune-timer-value = <8>;
276 #include "microcode/m0230671117.dtsi"
279 #include "microcode/m0130673325.dtsi"
282 #include "microcode/m0130679907.dtsi"