1 /* SPDX-License-Identifier: Intel */
3 * Copyright (C) 2013, Intel Corporation
4 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
6 * Ported from Intel released Quark UEFI BIOS
7 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
13 /* System Memory Controller Register Defines */
15 /* Memory Controller Message Bus Registers Offsets */
35 #define DECCSBECNT 0x62
36 #define DECCSBECA 0x68
37 #define DECCSBECS 0x69
38 #define DECCDBECA 0x6a
39 #define DECCDBECS 0x6b
40 #define DFUSESTAT 0x70
45 /* DRP register defines */
46 #define DRP_RKEN0 (1 << 0)
47 #define DRP_RKEN1 (1 << 1)
48 #define DRP_PRI64BSPLITEN (1 << 13)
49 #define DRP_ADDRMAP_MAP0 (1 << 14)
50 #define DRP_ADDRMAP_MAP1 (1 << 15)
51 #define DRP_ADDRMAP_MASK 0x0000c000
53 /* DTR0 register defines */
54 #define DTR0_DFREQ_MASK 0x00000003
55 #define DTR0_TRP_MASK 0x000000f0
56 #define DTR0_TRCD_MASK 0x00000f00
57 #define DTR0_TCL_MASK 0x00007000
59 /* DTR1 register defines */
60 #define DTR1_TWCL_MASK 0x00000007
61 #define DTR1_TCMD_MASK 0x00000030
62 #define DTR1_TWTP_MASK 0x00000f00
63 #define DTR1_TCCD_12CLK (1 << 12)
64 #define DTR1_TCCD_18CLK (1 << 13)
65 #define DTR1_TCCD_MASK 0x00003000
66 #define DTR1_TFAW_MASK 0x000f0000
67 #define DTR1_TRAS_MASK 0x00f00000
68 #define DTR1_TRRD_MASK 0x03000000
69 #define DTR1_TRTP_MASK 0x70000000
71 /* DTR2 register defines */
72 #define DTR2_TRRDR_MASK 0x00000007
73 #define DTR2_TWWDR_MASK 0x00000700
74 #define DTR2_TRWDR_MASK 0x000f0000
76 /* DTR3 register defines */
77 #define DTR3_TWRDR_MASK 0x00000007
78 #define DTR3_TXXXX_MASK 0x00000070
79 #define DTR3_TRWSR_MASK 0x00000f00
80 #define DTR3_TWRSR_MASK 0x0001e000
81 #define DTR3_TXP_MASK 0x00c00000
83 /* DTR4 register defines */
84 #define DTR4_WRODTSTRT_MASK 0x00000003
85 #define DTR4_WRODTSTOP_MASK 0x00000070
86 #define DTR4_XXXX1_MASK 0x00000700
87 #define DTR4_XXXX2_MASK 0x00007000
88 #define DTR4_ODTDIS (1 << 15)
89 #define DTR4_TRGSTRDIS (1 << 16)
91 /* DPMC0 register defines */
92 #define DPMC0_PCLSTO_MASK 0x00070000
93 #define DPMC0_PREAPWDEN (1 << 21)
94 #define DPMC0_DYNSREN (1 << 23)
95 #define DPMC0_CLKGTDIS (1 << 24)
96 #define DPMC0_DISPWRDN (1 << 25)
97 #define DPMC0_ENPHYCLKGATE (1 << 29)
99 /* DRFC register defines */
100 #define DRFC_TREFI_MASK 0x00007000
101 #define DRFC_REFDBTCLR (1 << 21)
103 /* DSCH register defines */
104 #define DSCH_OOODIS (1 << 8)
105 #define DSCH_OOOST3DIS (1 << 9)
106 #define DSCH_NEWBYPDIS (1 << 12)
108 /* DCAL register defines */
109 #define DCAL_ZQCINT_MASK 0x00000700
110 #define DCAL_SRXZQCL_MASK 0x00003000
112 /* DRMC register defines */
113 #define DRMC_CKEMODE (1 << 4)
114 #define DRMC_ODTMODE (1 << 12)
115 #define DRMC_COLDWAKE (1 << 16)
117 /* PMSTS register defines */
118 #define PMSTS_DISR (1 << 0)
120 /* DCO register defines */
121 #define DCO_DRPLOCK (1 << 0)
122 #define DCO_CPGCLOCK (1 << 8)
123 #define DCO_PMICTL (1 << 28)
124 #define DCO_PMIDIS (1 << 29)
125 #define DCO_IC (1 << 31)
127 /* DECCCTRL register defines */
128 #define DECCCTRL_SBEEN (1 << 0)
129 #define DECCCTRL_DBEEN (1 << 1)
130 #define DECCCTRL_ENCBGEN (1 << 17)
132 /* DRAM init command */
133 #define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
134 #define DCMD_REF(rnk) (1 | ((rnk) << 22))
135 #define DCMD_PRE(rnk) (2 | ((rnk) << 22))
136 #define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6))
137 #define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
138 #define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
139 #define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
140 #define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
141 #define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6))
142 #define DCMD_NOP(rnk) (7 | ((rnk) << 22))
144 #define DDR3_EMRS1_DIC_40 0
145 #define DDR3_EMRS1_DIC_34 1
147 #define DDR3_EMRS1_RTTNOM_0 0
148 #define DDR3_EMRS1_RTTNOM_60 0x04
149 #define DDR3_EMRS1_RTTNOM_120 0x40
150 #define DDR3_EMRS1_RTTNOM_40 0x44
151 #define DDR3_EMRS1_RTTNOM_20 0x200
152 #define DDR3_EMRS1_RTTNOM_30 0x204
154 #define DDR3_EMRS2_RTTWR_60 (1 << 9)
155 #define DDR3_EMRS2_RTTWR_120 (1 << 10)
157 /* BEGIN DDRIO Registers */
159 /* DDR IOs & COMPs */
160 #define DDRIODQ_BL_OFFSET 0x0800
161 #define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET)
162 #define DDRIOCCC_CH_OFFSET 0x0800
163 #define DDRCOMP_CH_OFFSET 0x0100
166 #define DQOBSCKEBBCTL 0x0000
167 #define DQDLLTXCTL 0x0004
168 #define DQDLLRXCTL 0x0008
169 #define DQMDLLCTL 0x000c
170 #define B0RXIOBUFCTL 0x0010
171 #define B0VREFCTL 0x0014
172 #define B0RXOFFSET1 0x0018
173 #define B0RXOFFSET0 0x001c
174 #define B1RXIOBUFCTL 0x0020
175 #define B1VREFCTL 0x0024
176 #define B1RXOFFSET1 0x0028
177 #define B1RXOFFSET0 0x002c
178 #define DQDFTCTL 0x0030
179 #define DQTRAINSTS 0x0034
180 #define B1DLLPICODER0 0x0038
181 #define B0DLLPICODER0 0x003c
182 #define B1DLLPICODER1 0x0040
183 #define B0DLLPICODER1 0x0044
184 #define B1DLLPICODER2 0x0048
185 #define B0DLLPICODER2 0x004c
186 #define B1DLLPICODER3 0x0050
187 #define B0DLLPICODER3 0x0054
188 #define B1RXDQSPICODE 0x0058
189 #define B0RXDQSPICODE 0x005c
190 #define B1RXDQPICODER32 0x0060
191 #define B1RXDQPICODER10 0x0064
192 #define B0RXDQPICODER32 0x0068
193 #define B0RXDQPICODER10 0x006c
194 #define B01PTRCTL0 0x0070
195 #define B01PTRCTL1 0x0074
196 #define B01DBCTL0 0x0078
197 #define B01DBCTL1 0x007c
198 #define B0LATCTL0 0x0080
199 #define B1LATCTL0 0x0084
200 #define B01LATCTL1 0x0088
201 #define B0ONDURCTL 0x008c
202 #define B1ONDURCTL 0x0090
203 #define B0OVRCTL 0x0094
204 #define B1OVRCTL 0x0098
206 #define B0RK2RKCHGPTRCTRL 0x00a0
207 #define B1RK2RKCHGPTRCTRL 0x00a4
208 #define DQRK2RKCTL 0x00a8
209 #define DQRK2RKPTRCTL 0x00ac
210 #define B0RK2RKLAT 0x00b0
211 #define B1RK2RKLAT 0x00b4
212 #define DQCLKALIGNREG0 0x00b8
213 #define DQCLKALIGNREG1 0x00bc
214 #define DQCLKALIGNREG2 0x00c0
215 #define DQCLKALIGNSTS0 0x00c4
216 #define DQCLKALIGNSTS1 0x00c8
217 #define DQCLKGATE 0x00cc
218 #define B0COMPSLV1 0x00d0
219 #define B1COMPSLV1 0x00d4
220 #define B0COMPSLV2 0x00d8
221 #define B1COMPSLV2 0x00dc
222 #define B0COMPSLV3 0x00e0
223 #define B1COMPSLV3 0x00e4
224 #define DQVISALANECR0TOP 0x00e8
225 #define DQVISALANECR1TOP 0x00ec
226 #define DQVISACONTROLCRTOP 0x00f0
227 #define DQVISALANECR0BL 0x00f4
228 #define DQVISALANECR1BL 0x00f8
229 #define DQVISACONTROLCRBL 0x00fc
230 #define DQTIMINGCTRL 0x010c
233 #define ECCDLLTXCTL 0x2004
234 #define ECCDLLRXCTL 0x2008
235 #define ECCMDLLCTL 0x200c
236 #define ECCB1DLLPICODER0 0x2038
237 #define ECCB1DLLPICODER1 0x2040
238 #define ECCB1DLLPICODER2 0x2048
239 #define ECCB1DLLPICODER3 0x2050
240 #define ECCB01DBCTL0 0x2078
241 #define ECCB01DBCTL1 0x207c
242 #define ECCCLKALIGNREG0 0x20b8
243 #define ECCCLKALIGNREG1 0x20bc
244 #define ECCCLKALIGNREG2 0x20c0
247 #define CMDOBSCKEBBCTL 0x4800
248 #define CMDDLLTXCTL 0x4808
249 #define CMDDLLRXCTL 0x480c
250 #define CMDMDLLCTL 0x4810
251 #define CMDRCOMPODT 0x4814
252 #define CMDDLLPICODER0 0x4820
253 #define CMDDLLPICODER1 0x4824
254 #define CMDCFGREG0 0x4840
255 #define CMDPTRREG 0x4844
256 #define CMDCLKALIGNREG0 0x4850
257 #define CMDCLKALIGNREG1 0x4854
258 #define CMDCLKALIGNREG2 0x4858
259 #define CMDPMCONFIG0 0x485c
260 #define CMDPMDLYREG0 0x4860
261 #define CMDPMDLYREG1 0x4864
262 #define CMDPMDLYREG2 0x4868
263 #define CMDPMDLYREG3 0x486c
264 #define CMDPMDLYREG4 0x4870
265 #define CMDCLKALIGNSTS0 0x4874
266 #define CMDCLKALIGNSTS1 0x4878
267 #define CMDPMSTS0 0x487c
268 #define CMDPMSTS1 0x4880
269 #define CMDCOMPSLV 0x4884
270 #define CMDBONUS0 0x488c
271 #define CMDBONUS1 0x4890
272 #define CMDVISALANECR0 0x4894
273 #define CMDVISALANECR1 0x4898
274 #define CMDVISACONTROLCR 0x489c
275 #define CMDCLKGATE 0x48a0
276 #define CMDTIMINGCTRL 0x48a4
279 #define CCOBSCKEBBCTL 0x5800
280 #define CCRCOMPIO 0x5804
281 #define CCDLLTXCTL 0x5808
282 #define CCDLLRXCTL 0x580c
283 #define CCMDLLCTL 0x5810
284 #define CCRCOMPODT 0x5814
285 #define CCDLLPICODER0 0x5820
286 #define CCDLLPICODER1 0x5824
287 #define CCDDR3RESETCTL 0x5830
288 #define CCCFGREG0 0x5838
289 #define CCCFGREG1 0x5840
290 #define CCPTRREG 0x5844
291 #define CCCLKALIGNREG0 0x5850
292 #define CCCLKALIGNREG1 0x5854
293 #define CCCLKALIGNREG2 0x5858
294 #define CCPMCONFIG0 0x585c
295 #define CCPMDLYREG0 0x5860
296 #define CCPMDLYREG1 0x5864
297 #define CCPMDLYREG2 0x5868
298 #define CCPMDLYREG3 0x586c
299 #define CCPMDLYREG4 0x5870
300 #define CCCLKALIGNSTS0 0x5874
301 #define CCCLKALIGNSTS1 0x5878
302 #define CCPMSTS0 0x587c
303 #define CCPMSTS1 0x5880
304 #define CCCOMPSLV1 0x5884
305 #define CCCOMPSLV2 0x5888
306 #define CCCOMPSLV3 0x588c
307 #define CCBONUS0 0x5894
308 #define CCBONUS1 0x5898
309 #define CCVISALANECR0 0x589c
310 #define CCVISALANECR1 0x58a0
311 #define CCVISACONTROLCR 0x58a4
312 #define CCCLKGATE 0x58a8
313 #define CCTIMINGCTL 0x58ac
316 #define CMPCTRL 0x6800
317 #define SOFTRSTCNTL 0x6804
318 #define MSCNTR 0x6808
319 #define NMSCNTRL 0x680c
320 #define LATCH1CTL 0x6814
321 #define COMPVISALANECR0 0x681c
322 #define COMPVISALANECR1 0x6820
323 #define COMPVISACONTROLCR 0x6824
324 #define COMPBONUS0 0x6830
325 #define TCOCNTCTRL 0x683c
326 #define DQANAODTPUCTL 0x6840
327 #define DQANAODTPDCTL 0x6844
328 #define DQANADRVPUCTL 0x6848
329 #define DQANADRVPDCTL 0x684c
330 #define DQANADLYPUCTL 0x6850
331 #define DQANADLYPDCTL 0x6854
332 #define DQANATCOPUCTL 0x6858
333 #define DQANATCOPDCTL 0x685c
334 #define CMDANADRVPUCTL 0x6868
335 #define CMDANADRVPDCTL 0x686c
336 #define CMDANADLYPUCTL 0x6870
337 #define CMDANADLYPDCTL 0x6874
338 #define CLKANAODTPUCTL 0x6880
339 #define CLKANAODTPDCTL 0x6884
340 #define CLKANADRVPUCTL 0x6888
341 #define CLKANADRVPDCTL 0x688c
342 #define CLKANADLYPUCTL 0x6890
343 #define CLKANADLYPDCTL 0x6894
344 #define CLKANATCOPUCTL 0x6898
345 #define CLKANATCOPDCTL 0x689c
346 #define DQSANAODTPUCTL 0x68a0
347 #define DQSANAODTPDCTL 0x68a4
348 #define DQSANADRVPUCTL 0x68a8
349 #define DQSANADRVPDCTL 0x68ac
350 #define DQSANADLYPUCTL 0x68b0
351 #define DQSANADLYPDCTL 0x68b4
352 #define DQSANATCOPUCTL 0x68b8
353 #define DQSANATCOPDCTL 0x68bc
354 #define CTLANADRVPUCTL 0x68c8
355 #define CTLANADRVPDCTL 0x68cc
356 #define CTLANADLYPUCTL 0x68d0
357 #define CTLANADLYPDCTL 0x68d4
358 #define CHNLBUFSTATIC 0x68f0
359 #define COMPOBSCNTRL 0x68f4
360 #define COMPBUFFDBG0 0x68f8
361 #define COMPBUFFDBG1 0x68fc
362 #define CFGMISCCH0 0x6900
363 #define COMPEN0CH0 0x6904
364 #define COMPEN1CH0 0x6908
365 #define COMPEN2CH0 0x690c
366 #define STATLEGEN0CH0 0x6910
367 #define STATLEGEN1CH0 0x6914
368 #define DQVREFCH0 0x6918
369 #define CMDVREFCH0 0x691c
370 #define CLKVREFCH0 0x6920
371 #define DQSVREFCH0 0x6924
372 #define CTLVREFCH0 0x6928
373 #define TCOVREFCH0 0x692c
374 #define DLYSELCH0 0x6930
375 #define TCODRAMBUFODTCH0 0x6934
376 #define CCBUFODTCH0 0x6938
377 #define RXOFFSETCH0 0x693c
378 #define DQODTPUCTLCH0 0x6940
379 #define DQODTPDCTLCH0 0x6944
380 #define DQDRVPUCTLCH0 0x6948
381 #define DQDRVPDCTLCH0 0x694c
382 #define DQDLYPUCTLCH0 0x6950
383 #define DQDLYPDCTLCH0 0x6954
384 #define DQTCOPUCTLCH0 0x6958
385 #define DQTCOPDCTLCH0 0x695c
386 #define CMDDRVPUCTLCH0 0x6968
387 #define CMDDRVPDCTLCH0 0x696c
388 #define CMDDLYPUCTLCH0 0x6970
389 #define CMDDLYPDCTLCH0 0x6974
390 #define CLKODTPUCTLCH0 0x6980
391 #define CLKODTPDCTLCH0 0x6984
392 #define CLKDRVPUCTLCH0 0x6988
393 #define CLKDRVPDCTLCH0 0x698c
394 #define CLKDLYPUCTLCH0 0x6990
395 #define CLKDLYPDCTLCH0 0x6994
396 #define CLKTCOPUCTLCH0 0x6998
397 #define CLKTCOPDCTLCH0 0x699c
398 #define DQSODTPUCTLCH0 0x69a0
399 #define DQSODTPDCTLCH0 0x69a4
400 #define DQSDRVPUCTLCH0 0x69a8
401 #define DQSDRVPDCTLCH0 0x69ac
402 #define DQSDLYPUCTLCH0 0x69b0
403 #define DQSDLYPDCTLCH0 0x69b4
404 #define DQSTCOPUCTLCH0 0x69b8
405 #define DQSTCOPDCTLCH0 0x69bc
406 #define CTLDRVPUCTLCH0 0x69c8
407 #define CTLDRVPDCTLCH0 0x69cc
408 #define CTLDLYPUCTLCH0 0x69d0
409 #define CTLDLYPDCTLCH0 0x69d4
410 #define FNLUPDTCTLCH0 0x69f0
413 #define MPLLCTRL0 0x7800
414 #define MPLLCTRL1 0x7808
415 #define MPLLCSR0 0x7810
416 #define MPLLCSR1 0x7814
417 #define MPLLCSR2 0x7820
418 #define MPLLDFT 0x7828
419 #define MPLLMON0CTL 0x7830
420 #define MPLLMON1CTL 0x7838
421 #define MPLLMON2CTL 0x783c
422 #define SFRTRIM 0x7850
423 #define MPLLDFTOUT0 0x7858
424 #define MPLLDFTOUT1 0x785c
425 #define MASTERRSTN 0x7880
426 #define PLLLOCKDEL 0x7884
427 #define SFRDEL 0x7888
428 #define CRUVISALANECR0 0x78f0
429 #define CRUVISALANECR1 0x78f4
430 #define CRUVISACONTROLCR 0x78f8
431 #define IOSFVISALANECR0 0x78fc
432 #define IOSFVISALANECR1 0x7900
433 #define IOSFVISACONTROLCR 0x7904
435 /* END DDRIO Registers */
437 /* DRAM Specific Message Bus OpCodes */
438 #define MSG_OP_DRAM_INIT 0x68
439 #define MSG_OP_DRAM_WAKE 0xca
441 #define SAMPLE_SIZE 6
443 /* must be less than this number to enable early deadband */
444 #define EARLY_DB 0x12
445 /* must be greater than this number to enable late deadband */
448 #define CHX_REGS (11 * 4)
453 #define MCEIL(num, den) ((uint8_t)((num + den - 1) / den))
454 #define MMAX(a, b) ((a) > (b) ? (a) : (b))
455 #define DEAD_LOOP() for (;;);
457 #define MIN_RDQS_EYE 10 /* in PI Codes */
458 #define MIN_VREF_EYE 10 /* in VREF Codes */
459 /* how many RDQS codes to jump while margining */
461 /* how many VREF codes to jump while margining */
463 /* offset into "vref_codes[]" for minimum allowed VREF setting */
464 #define VREF_MIN 0x00
465 /* offset into "vref_codes[]" for maximum allowed VREF setting */
466 #define VREF_MAX 0x3f
467 #define RDQS_MIN 0x00 /* minimum RDQS delay value */
468 #define RDQS_MAX 0x3f /* maximum RDQS delay value */
470 /* how many WDQ codes to jump while margining */
485 /* enable STATIC timing settings for RCVN (BACKUP_MODE) */
487 /* enable STATIC timing settings for WDQS (BACKUP_MODE) */
489 /* enable STATIC timing settings for RDQS (BACKUP_MODE) */
491 /* enable STATIC timing settings for WDQ (BACKUP_MODE) */
493 /* enable *COMP overrides (BACKUP_MODE) */
495 /* enable the RD_TRAIN eye check */
498 /* enable Host to Memory Clock Alignment */
500 /* enable multi-rank support via rank2rank sharing */
502 /* disable signals not used in 16bit mode of DDRIO */
503 #define FORCE_16BIT_DDRIO
505 #define PLATFORM_ID 1
507 void clear_self_refresh(struct mrc_params *mrc_params);
508 void prog_ddr_timing_control(struct mrc_params *mrc_params);
509 void prog_decode_before_jedec(struct mrc_params *mrc_params);
510 void perform_ddr_reset(struct mrc_params *mrc_params);
511 void ddrphy_init(struct mrc_params *mrc_params);
512 void perform_jedec_init(struct mrc_params *mrc_params);
513 void set_ddr_init_complete(struct mrc_params *mrc_params);
514 void restore_timings(struct mrc_params *mrc_params);
515 void default_timings(struct mrc_params *mrc_params);
516 void rcvn_cal(struct mrc_params *mrc_params);
517 void wr_level(struct mrc_params *mrc_params);
518 void prog_page_ctrl(struct mrc_params *mrc_params);
519 void rd_train(struct mrc_params *mrc_params);
520 void wr_train(struct mrc_params *mrc_params);
521 void store_timings(struct mrc_params *mrc_params);
522 void enable_scrambling(struct mrc_params *mrc_params);
523 void prog_ddr_control(struct mrc_params *mrc_params);
524 void prog_dra_drb(struct mrc_params *mrc_params);
525 void perform_wake(struct mrc_params *mrc_params);
526 void change_refresh_period(struct mrc_params *mrc_params);
527 void set_auto_refresh(struct mrc_params *mrc_params);
528 void ecc_enable(struct mrc_params *mrc_params);
529 void memory_test(struct mrc_params *mrc_params);
530 void lock_registers(struct mrc_params *mrc_params);