2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/ioapic.h>
11 #include <asm/mrccache.h>
15 #include <asm/arch/device.h>
16 #include <asm/arch/msg_port.h>
17 #include <asm/arch/quark.h>
19 static struct pci_device_id mmc_supported[] = {
20 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
24 static void quark_setup_mtrr(void)
31 /* mark the VGA RAM area as uncacheable */
32 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
33 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
34 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
35 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
37 /* mark other fixed range areas as cacheable */
38 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
39 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
40 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
41 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
42 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
43 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
44 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
45 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
46 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
47 msg_port_write(MSG_PORT_HOST_BRIDGE, i,
48 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
50 /* variable range MTRR#0: ROM area */
51 mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
52 base = CONFIG_SYS_TEXT_BASE & mask;
53 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
54 base | MTRR_TYPE_WRBACK);
55 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
56 mask | MTRR_PHYS_MASK_VALID);
58 /* variable range MTRR#1: eSRAM area */
59 mask = ~(ESRAM_SIZE - 1);
60 base = CONFIG_ESRAM_BASE & mask;
61 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
62 base | MTRR_TYPE_WRBACK);
63 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
64 mask | MTRR_PHYS_MASK_VALID);
66 /* enable both variable and fixed range MTRRs */
67 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
68 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
73 static void quark_setup_bars(void)
75 /* GPIO - D31:F0:R44h */
76 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
77 CONFIG_GPIO_BASE | IO_BAR_EN);
79 /* ACPI PM1 Block - D31:F0:R48h */
80 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
81 CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
83 /* GPE0 - D31:F0:R4Ch */
84 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
85 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
87 /* WDT - D31:F0:R84h */
88 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
89 CONFIG_WDT_BASE | IO_BAR_EN);
91 /* RCBA - D31:F0:RF0h */
92 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
93 CONFIG_RCBA_BASE | MEM_BAR_EN);
95 /* ACPI P Block - Msg Port 04:R70h */
96 msg_port_write(MSG_PORT_RMU, PBLK_BA,
97 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
99 /* SPI DMA - Msg Port 04:R7Ah */
100 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
101 CONFIG_SPI_DMA_BASE | IO_BAR_EN);
104 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
105 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
106 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
107 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
110 static void quark_pcie_early_init(void)
113 * Step1: Assert PCIe signal PERST#
115 * The CPU interface to the PERST# signal is platform dependent.
116 * Call the board-specific codes to perform this task.
118 board_assert_perst();
120 /* Step2: PHY common lane reset */
121 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
122 /* wait 1 ms for PHY common lane reset */
125 /* Step3: PHY sideband interface reset and controller main reset */
126 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
127 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
128 /* wait 80ms for PLL to lock */
131 /* Step4: Controller sideband interface reset */
132 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
133 /* wait 20ms for controller sideband interface reset */
136 /* Step5: De-assert PERST# */
137 board_deassert_perst();
139 /* Step6: Controller primary interface reset */
140 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
142 /* Mixer Load Lane 0 */
143 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
144 (1 << 6) | (1 << 7));
146 /* Mixer Load Lane 1 */
147 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
148 (1 << 6) | (1 << 7));
151 static void quark_usb_early_init(void)
153 /* The sequence below comes from Quark firmware writer guide */
155 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
156 1 << 1, (1 << 6) | (1 << 7));
158 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
159 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
161 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
163 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
165 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
166 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
168 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
170 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
173 static void quark_thermal_early_init(void)
175 /* The sequence below comes from Quark firmware writer guide */
177 /* thermal sensor mode config */
178 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
179 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
180 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
181 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
183 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
184 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
185 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
186 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
187 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
188 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
189 (1 << 8) | (1 << 9), 1 << 8);
190 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
191 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
192 0x7ff800, 0xc8 << 11);
194 /* thermal monitor catastrophic trip set point (105 celsius) */
195 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
197 /* thermal monitor catastrophic trip clear point (0 celsius) */
198 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
200 /* take thermal sensor out of reset */
201 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
203 /* enable thermal monitor */
204 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
206 /* lock all thermal configuration */
207 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
210 static void quark_enable_legacy_seg(void)
212 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
213 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
216 int arch_cpu_init(void)
220 post_code(POST_CPU_INIT);
222 ret = x86_cpu_init_f();
227 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
228 * are accessed indirectly via the message port and not the traditional
229 * MSR mechanism. Only UC, WT and WB cache types are supported.
234 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
235 * which need be initialized with suggested values
239 /* Initialize USB2 PHY */
240 quark_usb_early_init();
242 /* Initialize thermal sensor */
243 quark_thermal_early_init();
245 /* Turn on legacy segments (A/B/E/F) decode to system RAM */
246 quark_enable_legacy_seg();
251 int arch_cpu_init_dm(void)
254 * Initialize PCIe controller
256 * Quark SoC holds the PCIe controller in reset following a power on.
257 * U-Boot needs to release the PCIe controller from reset. The PCIe
258 * controller (D23:F0/F1) will not be visible in PCI configuration
259 * space and any access to its PCI configuration registers will cause
260 * system hang while it is held in reset.
262 quark_pcie_early_init();
267 int print_cpuinfo(void)
269 post_code(POST_CPU_INFO);
270 return default_print_cpuinfo();
273 void reset_cpu(ulong addr)
279 static void quark_pcie_init(void)
283 /* PCIe upstream non-posted & posted request size */
284 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
285 CCFG_UPRS | CCFG_UNRS);
286 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
287 CCFG_UPRS | CCFG_UNRS);
289 /* PCIe packet fast transmit mode (IPF) */
290 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
291 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
293 /* PCIe message bus idle counter (SBIC) */
294 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
296 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
297 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
299 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
302 static void quark_usb_init(void)
306 /* Change USB EHCI packet buffer OUT/IN threshold */
307 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
308 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
310 /* Disable USB device interrupts */
311 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
312 writel(0x7f, bar + USBD_INT_MASK);
313 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
314 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
317 int arch_early_init_r(void)
326 int cpu_mmc_init(bd_t *bis)
328 return pci_mmc_init("Quark SDHCI", mmc_supported);
331 int arch_misc_init(void)
333 #ifdef CONFIG_ENABLE_MRC_CACHE
335 * We intend not to check any return value here, as even MRC cache
336 * is not saved successfully, it is not a severe error that will
337 * prevent system from continuing to boot.
342 /* Assign a unique I/O APIC ID */
348 void board_final_cleanup(void)
350 struct quark_rcba *rcba;
353 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
355 rcba = (struct quark_rcba *)base;
357 /* Initialize 'Component ID' to zero */
358 val = readl(&rcba->esd);
360 writel(val, &rcba->esd);
362 /* Lock HMBOUND for security */
363 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);