2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/mrccache.h>
15 #include <asm/processor.h>
16 #include <asm/arch/device.h>
17 #include <asm/arch/msg_port.h>
18 #include <asm/arch/quark.h>
20 static struct pci_device_id mmc_supported[] = {
21 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
28 * This whole routine should be removed until we fully convert the ICH SPI
29 * driver to DM and make use of DT to pass the bios control register offset
31 static void unprotect_spi_flash(void)
35 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
36 bc |= 0x1; /* unprotect the flash */
37 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
40 static void quark_setup_mtrr(void)
47 /* mark the VGA RAM area as uncacheable */
48 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
49 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
50 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
51 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
53 /* mark other fixed range areas as cacheable */
54 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
55 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
56 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
57 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
58 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
59 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
60 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
61 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
62 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
63 msg_port_write(MSG_PORT_HOST_BRIDGE, i,
64 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
66 /* variable range MTRR#0: ROM area */
67 mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
68 base = CONFIG_SYS_TEXT_BASE & mask;
69 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
70 base | MTRR_TYPE_WRBACK);
71 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
72 mask | MTRR_PHYS_MASK_VALID);
74 /* variable range MTRR#1: eSRAM area */
75 mask = ~(ESRAM_SIZE - 1);
76 base = CONFIG_ESRAM_BASE & mask;
77 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
78 base | MTRR_TYPE_WRBACK);
79 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
80 mask | MTRR_PHYS_MASK_VALID);
82 /* enable both variable and fixed range MTRRs */
83 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
84 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
89 static void quark_setup_bars(void)
91 /* GPIO - D31:F0:R44h */
92 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
93 CONFIG_GPIO_BASE | IO_BAR_EN);
95 /* ACPI PM1 Block - D31:F0:R48h */
96 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
97 CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
99 /* GPE0 - D31:F0:R4Ch */
100 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
101 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
103 /* WDT - D31:F0:R84h */
104 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
105 CONFIG_WDT_BASE | IO_BAR_EN);
107 /* RCBA - D31:F0:RF0h */
108 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
109 CONFIG_RCBA_BASE | MEM_BAR_EN);
111 /* ACPI P Block - Msg Port 04:R70h */
112 msg_port_write(MSG_PORT_RMU, PBLK_BA,
113 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
115 /* SPI DMA - Msg Port 04:R7Ah */
116 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
117 CONFIG_SPI_DMA_BASE | IO_BAR_EN);
120 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
121 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
122 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
123 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
126 static void quark_pcie_early_init(void)
129 * Step1: Assert PCIe signal PERST#
131 * The CPU interface to the PERST# signal is platform dependent.
132 * Call the board-specific codes to perform this task.
134 board_assert_perst();
136 /* Step2: PHY common lane reset */
137 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
138 /* wait 1 ms for PHY common lane reset */
141 /* Step3: PHY sideband interface reset and controller main reset */
142 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
143 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
144 /* wait 80ms for PLL to lock */
147 /* Step4: Controller sideband interface reset */
148 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
149 /* wait 20ms for controller sideband interface reset */
152 /* Step5: De-assert PERST# */
153 board_deassert_perst();
155 /* Step6: Controller primary interface reset */
156 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
158 /* Mixer Load Lane 0 */
159 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
160 (1 << 6) | (1 << 7));
162 /* Mixer Load Lane 1 */
163 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
164 (1 << 6) | (1 << 7));
167 static void quark_usb_early_init(void)
169 /* The sequence below comes from Quark firmware writer guide */
171 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
172 1 << 1, (1 << 6) | (1 << 7));
174 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
175 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
177 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
179 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
181 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
182 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
184 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
186 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
189 static void quark_thermal_early_init(void)
191 /* The sequence below comes from Quark firmware writer guide */
193 /* thermal sensor mode config */
194 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
195 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
196 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
197 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
199 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
200 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
201 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
202 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
203 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
204 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
205 (1 << 8) | (1 << 9), 1 << 8);
206 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
207 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
208 0x7ff800, 0xc8 << 11);
210 /* thermal monitor catastrophic trip set point (105 celsius) */
211 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
213 /* thermal monitor catastrophic trip clear point (0 celsius) */
214 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
216 /* take thermal sensor out of reset */
217 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
219 /* enable thermal monitor */
220 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
222 /* lock all thermal configuration */
223 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
226 static void quark_enable_legacy_seg(void)
228 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
229 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
232 int arch_cpu_init(void)
236 post_code(POST_CPU_INIT);
238 ret = x86_cpu_init_f();
243 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
244 * are accessed indirectly via the message port and not the traditional
245 * MSR mechanism. Only UC, WT and WB cache types are supported.
250 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
251 * which need be initialized with suggested values
255 /* Initialize USB2 PHY */
256 quark_usb_early_init();
258 /* Initialize thermal sensor */
259 quark_thermal_early_init();
261 /* Turn on legacy segments (A/B/E/F) decode to system RAM */
262 quark_enable_legacy_seg();
264 unprotect_spi_flash();
269 int arch_cpu_init_dm(void)
272 * Initialize PCIe controller
274 * Quark SoC holds the PCIe controller in reset following a power on.
275 * U-Boot needs to release the PCIe controller from reset. The PCIe
276 * controller (D23:F0/F1) will not be visible in PCI configuration
277 * space and any access to its PCI configuration registers will cause
278 * system hang while it is held in reset.
280 quark_pcie_early_init();
285 int print_cpuinfo(void)
287 post_code(POST_CPU_INFO);
288 return default_print_cpuinfo();
291 void reset_cpu(ulong addr)
297 static void quark_pcie_init(void)
301 /* PCIe upstream non-posted & posted request size */
302 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
303 CCFG_UPRS | CCFG_UNRS);
304 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
305 CCFG_UPRS | CCFG_UNRS);
307 /* PCIe packet fast transmit mode (IPF) */
308 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
309 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
311 /* PCIe message bus idle counter (SBIC) */
312 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
314 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
315 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
317 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
320 static void quark_usb_init(void)
324 /* Change USB EHCI packet buffer OUT/IN threshold */
325 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
326 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
328 /* Disable USB device interrupts */
329 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
330 writel(0x7f, bar + USBD_INT_MASK);
331 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
332 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
335 int arch_early_init_r(void)
344 int cpu_mmc_init(bd_t *bis)
346 return pci_mmc_init("Quark SDHCI", mmc_supported);
349 void cpu_irq_init(void)
351 struct quark_rcba *rcba;
354 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
356 rcba = (struct quark_rcba *)base;
359 * Route Quark PCI device interrupt pin to PIRQ
361 * Route device#23's INTA/B/C/D to PIRQA/B/C/D
362 * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
364 writew(PIRQC, &rcba->rmu_ir);
365 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
367 writew(PIRQD, &rcba->core_ir);
368 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
372 int arch_misc_init(void)
374 #ifdef CONFIG_ENABLE_MRC_CACHE
376 * We intend not to check any return value here, as even MRC cache
377 * is not saved successfully, it is not a severe error that will
378 * prevent system from continuing to boot.
386 void board_final_cleanup(void)
388 struct quark_rcba *rcba;
391 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
393 rcba = (struct quark_rcba *)base;
395 /* Initialize 'Component ID' to zero */
396 val = readl(&rcba->esd);
398 writel(val, &rcba->esd);
400 /* Lock HMBOUND for security */
401 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
406 int reserve_arch(void)
408 #ifdef CONFIG_ENABLE_MRC_CACHE
409 return mrccache_reserve();