1 // SPDX-License-Identifier: Intel
3 * Copyright (C) 2013, Intel Corporation
4 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
6 * Ported from Intel released Quark UEFI BIOS
7 * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
11 #include <asm/arch/mrc.h>
12 #include <asm/arch/msg_port.h>
17 * Enable HTE to detect all possible errors for the given training parameters
18 * (per-bit or full byte lane).
20 static void hte_enable_all_errors(void)
22 msg_port_write(HTE, 0x000200a2, 0xffffffff);
23 msg_port_write(HTE, 0x000200a3, 0x000000ff);
24 msg_port_write(HTE, 0x000200a4, 0x00000000);
28 * Go and read the HTE register in order to find any error
30 * @return: The errors detected in the HTE status register
32 static u32 hte_check_errors(void)
34 return msg_port_read(HTE, 0x000200a7);
38 * Wait until HTE finishes
40 static void hte_wait_for_complete(void)
46 do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0);
48 tmp = msg_port_read(HTE, 0x00020011);
50 tmp &= ~((1 << 12) | (1 << 13));
51 msg_port_write(HTE, 0x00020011, tmp);
57 * Clear registers related with errors in the HTE
59 static void hte_clear_error_regs(void)
64 * Clear all HTE errors and enable error checking
65 * for burst and chunk.
67 tmp = msg_port_read(HTE, 0x000200a1);
69 msg_port_write(HTE, 0x000200a1, tmp);
73 * Execute a basic single-cache-line memory write/read/verify test using simple
74 * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
76 * See hte_basic_write_read() which is the external visible wrapper.
78 * @mrc_params: host structure for all MRC global data
79 * @addr: memory adress being tested (must hit specific channel/rank)
80 * @first_run: if set then the HTE registers are configured, otherwise it is
81 * assumed configuration is done and we just re-run the test
82 * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
84 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
86 static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
87 u8 first_run, u8 mode)
93 msg_port_write(HTE, 0x00020020, 0x01b10021);
94 msg_port_write(HTE, 0x00020021, 0x06000000);
95 msg_port_write(HTE, 0x00020022, addr >> 6);
96 msg_port_write(HTE, 0x00020062, 0x00800015);
97 msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
98 msg_port_write(HTE, 0x00020064, 0xcccccccc);
99 msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
100 msg_port_write(HTE, 0x00020061, 0x00030008);
102 if (mode == WRITE_TRAIN)
103 pattern = 0xc33c0000;
104 else /* READ_TRAIN */
105 pattern = 0xaa5555aa;
107 for (offset = 0x80; offset <= 0x8f; offset++)
108 msg_port_write(HTE, offset, pattern);
111 msg_port_write(HTE, 0x000200a1, 0xffff1000);
112 msg_port_write(HTE, 0x00020011, 0x00011000);
113 msg_port_write(HTE, 0x00020011, 0x00011100);
115 hte_wait_for_complete();
118 * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
119 * any bytelane errors.
121 return (hte_check_errors() >> 8) & 0xff;
125 * Examine a single-cache-line memory with write/read/verify test using multiple
126 * data patterns (victim-aggressor algorithm).
128 * See hte_write_stress_bit_lanes() which is the external visible wrapper.
130 * @mrc_params: host structure for all MRC global data
131 * @addr: memory adress being tested (must hit specific channel/rank)
132 * @loop_cnt: number of test iterations
133 * @seed_victim: victim data pattern seed
134 * @seed_aggressor: aggressor data pattern seed
135 * @victim_bit: should be 0 as auto-rotate feature is in use
136 * @first_run: if set then the HTE registers are configured, otherwise it is
137 * assumed configuration is done and we just re-run the test
139 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
141 static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
142 u8 loop_cnt, u32 seed_victim, u32 seed_aggressor,
143 u8 victim_bit, u8 first_run)
149 msg_port_write(HTE, 0x00020020, 0x00910024);
150 msg_port_write(HTE, 0x00020023, 0x00810024);
151 msg_port_write(HTE, 0x00020021, 0x06070000);
152 msg_port_write(HTE, 0x00020024, 0x06070000);
153 msg_port_write(HTE, 0x00020022, addr >> 6);
154 msg_port_write(HTE, 0x00020025, addr >> 6);
155 msg_port_write(HTE, 0x00020062, 0x0000002a);
156 msg_port_write(HTE, 0x00020063, seed_victim);
157 msg_port_write(HTE, 0x00020064, seed_aggressor);
158 msg_port_write(HTE, 0x00020065, seed_victim);
161 * Write the pattern buffers to select the victim bit
165 for (offset = 0x80; offset <= 0x8f; offset++) {
166 if ((offset % 8) == victim_bit)
167 msg_port_write(HTE, offset, 0x55555555);
169 msg_port_write(HTE, offset, 0xcccccccc);
172 msg_port_write(HTE, 0x00020061, 0x00000000);
173 msg_port_write(HTE, 0x00020066, 0x03440000);
174 msg_port_write(HTE, 0x000200a1, 0xffff1000);
177 tmp = 0x10001000 | (loop_cnt << 16);
178 msg_port_write(HTE, 0x00020011, tmp);
179 msg_port_write(HTE, 0x00020011, tmp | (1 << 8));
181 hte_wait_for_complete();
184 * Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
185 * any bytelane errors.
187 return (hte_check_errors() >> 8) & 0xff;
191 * Use HW HTE engine to initialize or test all memory attached to a given DUNIT.
192 * If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to
193 * initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5
194 * pattern to all memory locations on the RankMask and then read it back.
195 * Then it sends an A55AA55A pattern to all memory locations on the RankMask
198 * @mrc_params: host structure for all MRC global data
199 * @flag: MRC_MEM_INIT or MRC_MEM_TEST
201 * @return: errors register showing HTE failures. Also prints out which rank
202 * failed the HTE test if failure occurs. For rank detection to work,
203 * the address map must be left in its default state. If MRC changes
204 * the address map, this function must be modified to change it back
205 * to default at the beginning, then restore it at the end.
207 u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
214 * Clear out the error registers at the start of each memory
215 * init or memory test run.
217 hte_clear_error_regs();
219 msg_port_write(HTE, 0x00020062, 0x00000015);
221 for (offset = 0x80; offset <= 0x8f; offset++)
222 msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5));
224 msg_port_write(HTE, 0x00020021, 0x00000000);
225 msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
226 msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
227 msg_port_write(HTE, 0x00020064, 0xcccccccc);
228 msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
229 msg_port_write(HTE, 0x00020066, 0x03000000);
234 * Only 1 write pass through memory is needed
240 /* Write/read then write/read with inverted pattern */
244 DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
248 DPF(D_INFO, "hte_mem_init");
250 for (i = 0; i < test_num; i++) {
254 msg_port_write(HTE, 0x00020061, 0x00000000);
255 msg_port_write(HTE, 0x00020020, 0x00110010);
257 msg_port_write(HTE, 0x00020061, 0x00000000);
258 msg_port_write(HTE, 0x00020020, 0x00010010);
260 msg_port_write(HTE, 0x00020061, 0x00010100);
261 msg_port_write(HTE, 0x00020020, 0x00110010);
263 msg_port_write(HTE, 0x00020061, 0x00010100);
264 msg_port_write(HTE, 0x00020020, 0x00010010);
267 msg_port_write(HTE, 0x00020011, 0x00111000);
268 msg_port_write(HTE, 0x00020011, 0x00111100);
270 hte_wait_for_complete();
272 /* If this is a READ pass, check for errors at the end */
274 /* Return immediately if error */
275 if (hte_check_errors())
280 DPF(D_INFO, "done\n");
282 return hte_check_errors();
286 * Execute a basic single-cache-line memory write/read/verify test using simple
287 * constant pattern, different for READ_TRAIN and WRITE_TRAIN modes.
289 * @mrc_params: host structure for all MRC global data
290 * @addr: memory adress being tested (must hit specific channel/rank)
291 * @first_run: if set then the HTE registers are configured, otherwise it is
292 * assumed configuration is done and we just re-run the test
293 * @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern)
295 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
297 u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,
298 u8 first_run, u8 mode)
304 /* Enable all error reporting in preparation for HTE test */
305 hte_enable_all_errors();
306 hte_clear_error_regs();
308 errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode);
316 * Examine a single-cache-line memory with write/read/verify test using multiple
317 * data patterns (victim-aggressor algorithm).
319 * @mrc_params: host structure for all MRC global data
320 * @addr: memory adress being tested (must hit specific channel/rank)
321 * @first_run: if set then the HTE registers are configured, otherwise it is
322 * assumed configuration is done and we just re-run the test
324 * @return: byte lane failure on each bit (for Quark only bit0 and bit1)
326 u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params,
327 u32 addr, u8 first_run)
334 /* Enable all error reporting in preparation for HTE test */
335 hte_enable_all_errors();
336 hte_clear_error_regs();
339 * Loop through each bit in the bytelane.
341 * Each pass creates a victim bit while keeping all other bits the same
342 * as aggressors. AVN HTE adds an auto-rotate feature which allows us
343 * to program the entire victim/aggressor sequence in 1 step.
345 * The victim bit rotates on each pass so no need to have software
346 * implement a victim bit loop like on VLV.
348 errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT,
349 HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED,
350 victim_bit, first_run);
358 * Execute a basic single-cache-line memory write or read.
359 * This is just for receive enable / fine write-levelling purpose.
361 * @addr: memory adress being tested (must hit specific channel/rank)
362 * @first_run: if set then the HTE registers are configured, otherwise it is
363 * assumed configuration is done and we just re-run the test
364 * @is_write: when non-zero memory write operation executed, otherwise read
366 void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
371 hte_enable_all_errors();
372 hte_clear_error_regs();
375 tmp = is_write ? 0x01110021 : 0x01010021;
376 msg_port_write(HTE, 0x00020020, tmp);
378 msg_port_write(HTE, 0x00020021, 0x06000000);
379 msg_port_write(HTE, 0x00020022, addr >> 6);
380 msg_port_write(HTE, 0x00020062, 0x00800015);
381 msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
382 msg_port_write(HTE, 0x00020064, 0xcccccccc);
383 msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
384 msg_port_write(HTE, 0x00020061, 0x00030008);
386 for (offset = 0x80; offset <= 0x8f; offset++)
387 msg_port_write(HTE, offset, 0xc33c0000);
390 msg_port_write(HTE, 0x000200a1, 0xffff1000);
391 msg_port_write(HTE, 0x00020011, 0x00011000);
392 msg_port_write(HTE, 0x00020011, 0x00011100);
394 hte_wait_for_complete();