1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
12 #include <asm/mrccache.h>
15 #include <asm/arch/mrc.h>
16 #include <asm/arch/msg_port.h>
17 #include <asm/arch/quark.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
23 struct mrc_data_container *cache;
24 struct mrc_region entry;
27 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
31 cache = mrccache_find_current(&entry);
35 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
36 cache->data, cache->data_size, cache->checksum);
38 /* copy mrc cache to the mrc_params */
39 memcpy(&mrc_params->timings, cache->data, cache->data_size);
44 static int mrc_configure_params(struct mrc_params *mrc_params)
46 const void *blob = gd->fdt_blob;
50 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC);
52 debug("%s: Cannot find MRC node\n", __func__);
56 #ifdef CONFIG_ENABLE_MRC_CACHE
57 mrc_params->boot_mode = prepare_mrc_cache(mrc_params);
58 if (mrc_params->boot_mode)
59 mrc_params->boot_mode = BM_COLD;
61 mrc_params->boot_mode = BM_FAST;
63 mrc_params->boot_mode = BM_COLD;
69 * We need determine ECC by pin strap state
71 * Disable ECC by default for now
73 mrc_params->ecc_enables = 0;
75 mrc_flags = fdtdec_get_int(blob, node, "flags", 0);
76 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN)
77 mrc_params->scrambling_enables = 1;
79 mrc_params->scrambling_enables = 0;
81 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0);
82 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0);
83 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0);
85 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0);
86 mrc_params->channel_enables = fdtdec_get_int(blob, node,
88 mrc_params->channel_width = fdtdec_get_int(blob, node,
90 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0);
92 mrc_params->refresh_rate = fdtdec_get_int(blob, node,
94 mrc_params->sr_temp_range = fdtdec_get_int(blob, node,
96 mrc_params->ron_value = fdtdec_get_int(blob, node,
98 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node,
100 mrc_params->rd_odt_value = fdtdec_get_int(blob, node,
103 mrc_params->params.density = fdtdec_get_int(blob, node,
105 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
106 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0);
107 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0);
108 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0);
109 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0);
111 debug("MRC dram_width %d\n", mrc_params->dram_width);
112 debug("MRC rank_enables %d\n", mrc_params->rank_enables);
113 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed);
114 debug("MRC flags: %s\n",
115 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : "");
117 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",
118 mrc_params->params.density, mrc_params->params.cl,
119 mrc_params->params.ras, mrc_params->params.wtr,
120 mrc_params->params.rrd, mrc_params->params.faw);
127 struct mrc_params mrc_params;
128 #ifdef CONFIG_ENABLE_MRC_CACHE
133 memset(&mrc_params, 0, sizeof(struct mrc_params));
134 ret = mrc_configure_params(&mrc_params);
138 /* Set up the DRAM by calling the memory reference code */
139 mrc_init(&mrc_params);
140 if (mrc_params.status)
143 gd->ram_size = mrc_params.mem_size;
144 post_code(POST_DRAM);
146 /* variable range MTRR#2: RAM area */
148 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
149 0 | MTRR_TYPE_WRBACK);
150 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
151 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
154 #ifdef CONFIG_ENABLE_MRC_CACHE
155 cache = malloc(sizeof(struct mrc_timings));
157 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
159 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
161 mrc->len = sizeof(struct mrc_timings);
168 int dram_init_banksize(void)
170 gd->bd->bi_dram[0].start = 0;
171 gd->bd->bi_dram[0].size = gd->ram_size;
177 * This function looks for the highest region of memory lower than 4GB which
178 * has enough space for U-Boot where U-Boot is aligned on a page boundary.
179 * It overrides the default implementation found elsewhere which simply
180 * picks the end of ram, wherever that may be. The location of the stack,
181 * the relocation address, and how far U-Boot is moved by relocation are
182 * set in the global data structure.
184 ulong board_get_usable_ram_top(ulong total_size)