1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
9 #include <asm/arch/quark.h>
10 #include <asm/arch/msg_port.h>
14 post_code(POST_CAR_START)
17 * Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
18 * initialized by hardware. eSRAM is the ideal place to be used
19 * for Cache-As-RAM (CAR) before system memory is available.
21 * Relocate this eSRAM to a suitable location in the physical
22 * memory map and enable it.
25 /* Host Memory Bound Register P03h:R08h */
26 mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax
27 mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx
32 /* eSRAM Block Page Control Register P05h:R82h */
33 mov $((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax
34 mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx
39 post_code(POST_CAR_CPU_CACHE)
45 * eax[23:16] - Message Port ID
46 * eax[15:08] - Register Address
49 * eax - Message Port Register value
54 or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax
57 /* Write MCR B0:D0:F0:RD0 */
58 mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
59 mov $PCI_REG_ADDR, %dx
61 mov $PCI_REG_DATA, %dx
65 /* Read MDR B0:D0:F0:RD4 */
66 mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
67 mov $PCI_REG_ADDR, %dx
69 mov $PCI_REG_DATA, %dx
77 * eax[23:16] - Message Port ID
78 * eax[15:08] - Register Address
79 * edx - Message Port Register value to write
84 or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax
88 /* Write MDR B0:D0:F0:RD4 */
89 mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
90 mov $PCI_REG_ADDR, %dx
92 mov $PCI_REG_DATA, %dx
96 /* Write MCR B0:D0:F0:RD0 */
97 mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
98 mov $PCI_REG_ADDR, %dx
100 mov $PCI_REG_DATA, %dx