2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/quark.h>
11 #include <asm/arch/msg_port.h>
15 post_code(POST_CAR_START)
18 * Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
19 * initialized by hardware. eSRAM is the ideal place to be used
20 * for Cache-As-RAM (CAR) before system memory is available.
22 * Relocate this eSRAM to a suitable location in the physical
23 * memory map and enable it.
26 /* Host Memory Bound Register P03h:R08h */
27 mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax
28 mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx
33 /* eSRAM Block Page Control Register P05h:R82h */
34 mov $((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax
35 mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx
40 post_code(POST_CAR_CPU_CACHE)
46 * eax[23:16] - Message Port ID
47 * eax[15:08] - Register Address
50 * eax - Message Port Register value
55 or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax
58 /* Write MCR B0:D0:F0:RD0 */
59 mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
60 mov $PCI_REG_ADDR, %dx
62 mov $PCI_REG_DATA, %dx
66 /* Read MDR B0:D0:F0:RD4 */
67 mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
68 mov $PCI_REG_ADDR, %dx
70 mov $PCI_REG_DATA, %dx
78 * eax[23:16] - Message Port ID
79 * eax[15:08] - Register Address
80 * edx - Message Port Register value to write
85 or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax
89 /* Write MDR B0:D0:F0:RD4 */
90 mov $(PCI_CFG_EN | MSG_DATA_REG), %eax
91 mov $PCI_REG_ADDR, %dx
93 mov $PCI_REG_DATA, %dx
97 /* Write MCR B0:D0:F0:RD0 */
98 mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax
99 mov $PCI_REG_ADDR, %dx
101 mov $PCI_REG_DATA, %dx