2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/processor.h>
12 #include <asm/arch/device.h>
13 #include <asm/arch/qemu.h>
17 static void qemu_chipset_init(void)
23 * i440FX and Q35 chipset have different PAM register offset, but with
24 * the same bitfield layout. Here we determine the offset based on its
27 device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
28 i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
29 pam = i440fx ? I440FX_PAM : Q35_PAM;
32 * Initialize Programmable Attribute Map (PAM) Registers
34 * Configure legacy segments C/D/E/F to system RAM
36 for (i = 0; i < PAM_NUM; i++)
37 x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
41 * Enable legacy IDE I/O ports decode
43 * Note: QEMU always decode legacy IDE I/O port on PIIX chipset.
44 * However Linux ata_piix driver does sanity check on these two
45 * registers to see whether legacy ports decode is turned on.
46 * This is to make Linux ata_piix driver happy.
48 x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
49 x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
52 xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
54 x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
56 /* Configure PCIe ECAM base address */
57 x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR,
58 CONFIG_PCIE_ECAM_BASE | BAR_EN);
62 int arch_cpu_init(void)
66 post_code(POST_CPU_INIT);
67 #ifdef CONFIG_SYS_X86_TSC_TIMER
68 timer_set_base(rdtsc());
71 ret = x86_cpu_init_f();
78 #ifndef CONFIG_EFI_STUB
79 int print_cpuinfo(void)
81 post_code(POST_CPU_INFO);
82 return default_print_cpuinfo();
86 void reset_cpu(ulong addr)
92 int arch_early_init_r(void)
99 int arch_misc_init(void)
104 #ifdef CONFIG_GENERATE_MP_TABLE
105 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
111 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
112 * connected to I/O APIC INTPIN#16-19. Instead they are routed
113 * to an irq number controled by the PIRQ routing register.
115 irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
119 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
120 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
122 irq = pirq < 8 ? pirq + 16 : pirq + 12;