1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Prepare to adjust MTRRs */
27 void mtrr_open(struct mtrr_state *state, bool do_caches)
29 if (!gd->arch.has_mtrr)
33 state->enable_cache = dcache_status();
35 if (state->enable_cache)
38 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
39 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
42 /* Clean up after adjusting MTRRs, and enable them */
43 void mtrr_close(struct mtrr_state *state, bool do_caches)
45 if (!gd->arch.has_mtrr)
48 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
49 if (do_caches && state->enable_cache)
53 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
57 wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
59 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
60 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
63 int mtrr_commit(bool do_caches)
65 struct mtrr_request *req = gd->arch.mtrr_req;
66 struct mtrr_state state;
69 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
70 gd->arch.mtrr_req_count);
71 if (!gd->arch.has_mtrr)
75 mtrr_open(&state, do_caches);
77 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
78 set_var_mtrr(i, req->type, req->start, req->size);
80 /* Clear the ones that are unused */
82 for (; i < MTRR_COUNT; i++)
83 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
85 mtrr_close(&state, do_caches);
91 int mtrr_add_request(int type, uint64_t start, uint64_t size)
93 struct mtrr_request *req;
96 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
97 if (!gd->arch.has_mtrr)
100 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
102 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
106 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
107 req->type, req->start, req->size);
108 mask = ~(req->size - 1);
109 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
110 mask |= MTRR_PHYS_MASK_VALID;
111 debug(" %016llx %016llx\n", req->start | req->type, mask);
116 static int get_var_mtrr_count(void)
118 return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
121 static int get_free_var_mtrr(void)
127 vcnt = get_var_mtrr_count();
129 /* Identify the first var mtrr which is not valid */
130 for (i = 0; i < vcnt; i++) {
131 maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
132 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
136 /* No free var mtrr */
140 int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
144 mtrr = get_free_var_mtrr();
148 set_var_mtrr(mtrr, type, start, size);
149 debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);