1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
25 DECLARE_GLOBAL_DATA_PTR;
27 /* Prepare to adjust MTRRs */
28 void mtrr_open(struct mtrr_state *state, bool do_caches)
30 if (!gd->arch.has_mtrr)
34 state->enable_cache = dcache_status();
36 if (state->enable_cache)
39 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
40 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
43 /* Clean up after adjusting MTRRs, and enable them */
44 void mtrr_close(struct mtrr_state *state, bool do_caches)
46 if (!gd->arch.has_mtrr)
49 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
50 if (do_caches && state->enable_cache)
54 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
58 wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
60 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
61 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
64 int mtrr_commit(bool do_caches)
66 struct mtrr_request *req = gd->arch.mtrr_req;
67 struct mtrr_state state;
70 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
71 gd->arch.mtrr_req_count);
72 if (!gd->arch.has_mtrr)
76 mtrr_open(&state, do_caches);
78 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
79 set_var_mtrr(i, req->type, req->start, req->size);
81 /* Clear the ones that are unused */
83 for (; i < MTRR_COUNT; i++)
84 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
86 mtrr_close(&state, do_caches);
92 int mtrr_add_request(int type, uint64_t start, uint64_t size)
94 struct mtrr_request *req;
97 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
98 if (!gd->arch.has_mtrr)
101 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
103 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
107 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
108 req->type, req->start, req->size);
109 mask = ~(req->size - 1);
110 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
111 mask |= MTRR_PHYS_MASK_VALID;
112 debug(" %016llx %016llx\n", req->start | req->type, mask);
117 static int get_var_mtrr_count(void)
119 return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
122 static int get_free_var_mtrr(void)
128 vcnt = get_var_mtrr_count();
130 /* Identify the first var mtrr which is not valid */
131 for (i = 0; i < vcnt; i++) {
132 maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
133 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
137 /* No free var mtrr */
141 int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
145 mtrr = get_free_var_mtrr();
149 set_var_mtrr(mtrr, type, start, size);
150 debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);