3 * Copyright (C) 2008-2009 coresystems GmbH
5 * SPDX-License-Identifier: GPL-2.0
12 #include <asm/arch/pch.h>
13 #include <asm/arch/bd82x6x.h>
15 static inline u32 sir_read(pci_dev_t dev, int idx)
17 pci_write_config32(dev, SATA_SIRI, idx);
18 return pci_read_config32(dev, SATA_SIRD);
21 static inline void sir_write(pci_dev_t dev, int idx, u32 value)
23 pci_write_config32(dev, SATA_SIRI, idx);
24 pci_write_config32(dev, SATA_SIRD, value);
27 static void common_sata_init(pci_dev_t dev, unsigned int port_map)
32 /* Set IDE I/O Configuration */
33 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
34 pci_write_config32(dev, IDE_CONFIG, reg32);
37 reg16 = pci_read_config16(dev, 0x92);
40 pci_write_config16(dev, 0x92, reg16);
42 /* SATA Initialization register */
44 pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
47 void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
49 unsigned int port_map, speed_support, port_tx;
50 struct pci_controller *hose = pci_bus_to_hose(0);
55 debug("SATA: Initializing...\n");
57 /* SATA configuration */
58 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
59 speed_support = fdtdec_get_int(blob, node,
60 "sata_interface_speed_support", 0);
63 pci_write_config16(dev, PCI_COMMAND, 0x0007);
65 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
66 if (!mode || !strcmp(mode, "ahci")) {
69 debug("SATA: Controller in AHCI mode\n");
71 /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
72 pci_write_config8(dev, INTR_LN, 0x0a);
75 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
76 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
77 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
78 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
79 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
82 pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
83 pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
85 common_sata_init(dev, 0x8000 | port_map);
87 /* Initialize AHCI memory-mapped space */
88 abar = pci_read_bar32(hose, dev, 5);
89 debug("ABAR: %08X\n", abar);
90 /* CAP (HBA Capabilities) : enable power management */
91 reg32 = readl(abar + 0x00);
92 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */
93 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
94 /* Set ISS, if available */
97 reg32 |= (speed_support & 0x03) << 20;
99 writel(reg32, abar + 0x00);
100 /* PI (Ports implemented) */
101 writel(port_map, abar + 0x0c);
102 (void) readl(abar + 0x0c); /* Read back 1 */
103 (void) readl(abar + 0x0c); /* Read back 2 */
104 /* CAP2 (HBA Capabilities Extended)*/
105 reg32 = readl(abar + 0x24);
106 reg32 &= ~0x00000002;
107 writel(reg32, abar + 0x24);
108 /* VSP (Vendor Specific Register */
109 reg32 = readl(abar + 0xa0);
110 reg32 &= ~0x00000005;
111 writel(reg32, abar + 0xa0);
112 } else if (!strcmp(mode, "combined")) {
113 debug("SATA: Controller in combined mode\n");
115 /* No AHCI: clear AHCI base */
116 pci_write_bar32(hose, dev, 5, 0x00000000);
117 /* And without AHCI BAR no memory decoding */
118 reg16 = pci_read_config16(dev, PCI_COMMAND);
119 reg16 &= ~PCI_COMMAND_MEMORY;
120 pci_write_config16(dev, PCI_COMMAND, reg16);
122 pci_write_config8(dev, 0x09, 0x80);
125 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
126 IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
127 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
128 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
129 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
132 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
133 pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
135 common_sata_init(dev, port_map);
137 debug("SATA: Controller in plain-ide mode\n");
139 /* No AHCI: clear AHCI base */
140 pci_write_bar32(hose, dev, 5, 0x00000000);
142 /* And without AHCI BAR no memory decoding */
143 reg16 = pci_read_config16(dev, PCI_COMMAND);
144 reg16 &= ~PCI_COMMAND_MEMORY;
145 pci_write_config16(dev, PCI_COMMAND, reg16);
148 * Native mode capable on both primary and secondary (0xa)
149 * OR'ed with enabled (0x50) = 0xf
151 pci_write_config8(dev, 0x09, 0x8f);
153 /* Set Interrupt Line */
154 /* Interrupt Pin is set by D31IP.PIP */
155 pci_write_config8(dev, INTR_LN, 0xff);
158 pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
159 IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
160 IDE_PPE0 | IDE_IE0 | IDE_TIME0);
161 pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
162 IDE_SITRE | IDE_ISP_3_CLOCKS |
163 IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
166 pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
167 pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
169 common_sata_init(dev, port_map);
172 /* Set Gen3 Transmitter settings if needed */
173 port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
175 pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
177 port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
179 pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
181 /* Additional Programming Requirements */
182 sir_write(dev, 0x04, 0x00001600);
183 sir_write(dev, 0x28, 0xa0000033);
184 reg32 = sir_read(dev, 0x54);
187 sir_write(dev, 0x54, reg32);
188 sir_write(dev, 0x64, 0xcccc8484);
189 reg32 = sir_read(dev, 0x68);
192 sir_write(dev, 0x68, reg32);
193 reg32 = sir_read(dev, 0x78);
196 sir_write(dev, 0x78, reg32);
197 sir_write(dev, 0x84, 0x001c7000);
198 sir_write(dev, 0x88, 0x88338822);
199 sir_write(dev, 0xa0, 0x001c7000);
200 sir_write(dev, 0xc4, 0x0c0c0c0c);
201 sir_write(dev, 0xc8, 0x0c0c0c0c);
202 sir_write(dev, 0xd4, 0x10000000);
204 pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
205 pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
208 void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
215 * Set SATA controller mode early so the resource allocator can
216 * properly assign IO/Memory resources for the controller.
218 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
219 if (mode && !strcmp(mode, "ahci"))
221 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
223 map |= (port_map ^ 0x3f) << 8;
224 pci_write_config16(dev, 0x90, map);