2 * Copyright (c) 2014 Google, Inc
3 * Copyright (C) 2000 Ronald G. Minnich
5 * Microcode update for Intel PIII and later CPUs
7 * SPDX-License-Identifier: GPL-2.0
16 #include <asm/msr-index.h>
17 #include <asm/processor.h>
18 #include <asm/arch/microcode.h>
21 * struct microcode_update - standard microcode header from Intel
23 * We read this information out of the device tree and use it to determine
24 * whether the update is applicable or not. We also use the same structure
25 * to read information from the CPU.
27 struct microcode_update {
31 uint processor_signature;
39 static int microcode_decode_node(const void *blob, int node,
40 struct microcode_update *update)
42 update->data = fdt_getprop(blob, node, "data", &update->size);
45 update->data += UCODE_HEADER_LEN;
46 update->size -= UCODE_HEADER_LEN;
48 update->header_version = fdtdec_get_int(blob, node,
49 "intel,header-version", 0);
50 update->update_revision = fdtdec_get_int(blob, node,
51 "intel,update-revision", 0);
52 update->date_code = fdtdec_get_int(blob, node,
53 "intel,date-code", 0);
54 update->processor_signature = fdtdec_get_int(blob, node,
55 "intel,processor-signature", 0);
56 update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
57 update->loader_revision = fdtdec_get_int(blob, node,
58 "intel,loader-revision", 0);
59 update->processor_flags = fdtdec_get_int(blob, node,
60 "intel,processor-flags", 0);
65 static inline uint32_t microcode_read_rev(void)
68 * Some Intel CPUs can be very finicky about the CPUID sequence used.
69 * So this is implemented in assembly so that it works reliably.
83 "=a" (low), "=d" (high)
85 "i" (MSR_IA32_UCODE_REV)
93 static void microcode_read_cpu(struct microcode_update *cpu)
95 /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
96 unsigned int x86_model, x86_family;
97 struct cpuid_result result;
100 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
102 rdmsr(MSR_IA32_UCODE_REV, low, cpu->update_revision);
103 x86_model = (result.eax >> 4) & 0x0f;
104 x86_family = (result.eax >> 8) & 0x0f;
105 cpu->processor_signature = result.eax;
107 cpu->processor_flags = 0;
108 if ((x86_model >= 5) || (x86_family > 6)) {
109 rdmsr(0x17, low, high);
110 cpu->processor_flags = 1 << ((high >> 18) & 7);
112 debug("microcode: sig=%#x pf=%#x revision=%#x\n",
113 cpu->processor_signature, cpu->processor_flags,
114 cpu->update_revision);
117 /* Get a microcode update from the device tree and apply it */
118 int microcode_update_intel(void)
120 struct microcode_update cpu, update;
121 const void *blob = gd->fdt_blob;
128 microcode_read_cpu(&cpu);
133 node = fdtdec_next_compatible(blob, node,
134 COMPAT_INTEL_MICROCODE);
136 debug("%s: Found %d updates\n", __func__, count);
137 return count ? 0 : skipped ? -EEXIST : -ENOENT;
140 ret = microcode_decode_node(blob, node, &update);
142 debug("%s: Unable to decode update: %d\n", __func__,
146 if (!(update.processor_signature == cpu.processor_signature &&
147 (update.processor_flags & cpu.processor_flags))) {
148 debug("%s: Skipping non-matching update, sig=%x, pf=%x\n",
149 __func__, update.processor_signature,
150 update.processor_flags);
154 wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0);
155 rev = microcode_read_rev();
156 debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
157 rev, update.date_code & 0xffff,
158 (update.date_code >> 24) & 0xff,
159 (update.date_code >> 16) & 0xff);
160 if (update.update_revision != rev) {
161 printf("Microcode update failed\n");