4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2011 Google Inc
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/pch.h>
14 #include <asm/arch/sandybridge.h>
16 static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
18 /* Setting up Southbridge. In the northbridge code. */
19 debug("Setting up static southbridge registers\n");
20 x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
22 x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
23 x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
25 debug("Disabling watchdog reboot\n");
26 setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
27 outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
29 /* Set up all hardcoded northbridge BARs */
30 debug("Setting up static registers\n");
31 x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
32 x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
33 x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
34 x86_pci_write_config32(pch_dev, MCHBAR + 4,
35 (0LL + DEFAULT_MCHBAR) >> 32);
36 /* 64MB - busses 0-63 */
37 x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
38 x86_pci_write_config32(pch_dev, PCIEXBAR + 4,
39 (0LL + DEFAULT_PCIEXBAR) >> 32);
40 x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
41 x86_pci_write_config32(pch_dev, DMIBAR + 4,
42 (0LL + DEFAULT_DMIBAR) >> 32);
44 /* Set C0000-FFFFF to access RAM on both reads and writes */
45 x86_pci_write_config8(pch_dev, PAM0, 0x30);
46 x86_pci_write_config8(pch_dev, PAM1, 0x33);
47 x86_pci_write_config8(pch_dev, PAM2, 0x33);
48 x86_pci_write_config8(pch_dev, PAM3, 0x33);
49 x86_pci_write_config8(pch_dev, PAM4, 0x33);
50 x86_pci_write_config8(pch_dev, PAM5, 0x33);
51 x86_pci_write_config8(pch_dev, PAM6, 0x33);
54 static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
60 reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
62 case 0x0102: /* GT1 Desktop */
63 case 0x0106: /* GT1 Mobile */
64 case 0x010a: /* GT1 Server */
65 case 0x0112: /* GT2 Desktop */
66 case 0x0116: /* GT2 Mobile */
67 case 0x0122: /* GT2 Desktop >=1.3GHz */
68 case 0x0126: /* GT2 Mobile >=1.3GHz */
69 case 0x0156: /* IvyBridge */
70 case 0x0166: /* IvyBridge */
73 debug("Graphics not supported by this CPU/chipset\n");
77 debug("Initialising Graphics\n");
79 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
80 reg16 = x86_pci_read_config16(pch_dev, GGC);
83 /* Program GTT memory by setting GGC[9:8] = 2MB */
86 /* Enable VGA decode */
88 x86_pci_write_config16(pch_dev, GGC, reg16);
90 /* Enable 256MB aperture */
91 reg8 = x86_pci_read_config8(video_dev, MSAC);
94 x86_pci_write_config8(video_dev, MSAC, reg8);
96 /* Erratum workarounds */
97 reg32 = readl(MCHBAR_REG(0x5f00));
98 reg32 |= (1 << 9) | (1 << 10);
99 writel(reg32, MCHBAR_REG(0x5f00));
101 /* Enable SA Clock Gating */
102 reg32 = readl(MCHBAR_REG(0x5f00));
103 writel(reg32 | 1, MCHBAR_REG(0x5f00));
105 /* GPU RC6 workaround for sighting 366252 */
106 reg32 = readl(MCHBAR_REG(0x5d14));
108 writel(reg32, MCHBAR_REG(0x5d14));
111 reg32 = readl(MCHBAR_REG(0x6120));
113 writel(reg32, MCHBAR_REG(0x6120));
115 reg32 = readl(MCHBAR_REG(0x5418));
116 reg32 |= (1 << 4) | (1 << 5);
117 writel(reg32, MCHBAR_REG(0x5418));
120 void sandybridge_early_init(int chipset_type)
122 pci_dev_t pch_dev = PCH_DEV;
123 pci_dev_t video_dev = PCH_VIDEO_DEV;
124 pci_dev_t lpc_dev = PCH_LPC_DEV;
128 /* Device ID Override Enable should be done very early */
129 capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
130 if (capid0_a & (1 << 10)) {
131 reg8 = x86_pci_read_config8(pch_dev, 0xf3);
132 reg8 &= ~7; /* Clear 2:0 */
134 if (chipset_type == SANDYBRIDGE_MOBILE)
135 reg8 |= 1; /* Set bit 0 */
137 x86_pci_write_config8(pch_dev, 0xf3, reg8);
140 /* Setup all BARs required for early PCIe and raminit */
141 sandybridge_setup_bars(pch_dev, lpc_dev);
144 x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
146 sandybridge_setup_graphics(pch_dev, video_dev);