2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/intel_regs.h>
15 #include <asm/lapic.h>
16 #include <asm/lpc_common.h>
18 #include <asm/arch/model_206ax.h>
19 #include <asm/arch/pch.h>
20 #include <asm/arch/sandybridge.h>
22 #define GPIO_BASE 0x48
23 #define BIOS_CTRL 0xdc
25 #ifndef CONFIG_HAVE_FSP
26 static int pch_revision_id = -1;
27 static int pch_type = -1;
30 * pch_silicon_revision() - Read silicon revision ID from the PCH
33 * @return silicon revision ID
35 static int pch_silicon_revision(struct udevice *dev)
39 if (pch_revision_id < 0) {
40 dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
41 pch_revision_id = val;
44 return pch_revision_id;
47 int pch_silicon_type(struct udevice *dev)
52 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
60 * pch_silicon_supported() - Check if a certain revision is supported
64 * @rev: Minimum required resion
65 * @return 0 if not supported, 1 if supported
67 static int pch_silicon_supported(struct udevice *dev, int type, int rev)
69 int cur_type = pch_silicon_type(dev);
70 int cur_rev = pch_silicon_revision(dev);
74 /* CougarPoint minimum revision */
75 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
77 /* PantherPoint any revision */
78 if (cur_type == PCH_TYPE_PPT)
83 /* PantherPoint minimum revision */
84 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
92 #define IOBP_RETRY 1000
93 static inline int iobp_poll(void)
95 unsigned try = IOBP_RETRY;
99 data = readl(RCB_REG(IOBPS));
105 printf("IOBP timeout\n");
109 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
114 /* Set the address */
115 writel(address, RCB_REG(IOBPIRI));
118 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
119 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
121 writel(IOBPS_READ_AX, RCB_REG(IOBPS));
126 data = readl(RCB_REG(IOBPD));
130 /* Check for successful transaction */
131 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
132 printf("IOBP read 0x%08x failed\n", address);
136 /* Update the data */
141 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
142 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
144 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
148 /* Write IOBP data */
149 writel(data, RCB_REG(IOBPD));
154 static int bd82x6x_probe(struct udevice *dev)
156 if (!(gd->flags & GD_FLG_RELOC))
159 /* Cause the SATA device to do its init */
160 uclass_first_device(UCLASS_AHCI, &dev);
164 #endif /* CONFIG_HAVE_FSP */
166 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
170 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
171 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
172 rcba = rcba & 0xffffc000;
173 *sbasep = rcba + 0x3800;
178 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
180 return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
183 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
188 * GPIO_BASE moved to its current offset with ICH6, but prior to
189 * that it was unused (or undocumented). Check that it looks
190 * okay: not all ones or zeros.
192 * Note we don't need check bit0 here, because the Tunnel Creek
193 * GPIO base address register bit0 is reserved (read returns 0),
194 * while on the Ivybridge the bit0 is used to indicate it is an
197 dm_pci_read_config32(dev, GPIO_BASE, &base);
198 if (base == 0x00000000 || base == 0xffffffff) {
199 debug("%s: unexpected BASE value\n", __func__);
204 * Okay, I guess we're looking at the right device. The actual
205 * GPIO registers are in the PCI device's I/O space, starting
206 * at the offset that we just read. Bit 0 indicates that it's
207 * an I/O address, not a memory address, so mask that off.
209 *gbasep = base & 1 ? base & ~3 : base & ~15;
214 static const struct pch_ops bd82x6x_pch_ops = {
215 .get_spi_base = bd82x6x_pch_get_spi_base,
216 .set_spi_protect = bd82x6x_set_spi_protect,
217 .get_gpio_base = bd82x6x_get_gpio_base,
220 static const struct udevice_id bd82x6x_ids[] = {
221 { .compatible = "intel,bd82x6x" },
225 U_BOOT_DRIVER(bd82x6x_drv) = {
228 .of_match = bd82x6x_ids,
229 #ifndef CONFIG_HAVE_FSP
230 .probe = bd82x6x_probe,
232 .ops = &bd82x6x_pch_ops,