2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/pirq_routing.h>
16 #include <asm/tables.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
22 struct irq_router *priv = dev_get_priv(dev);
24 int base = priv->link_base;
26 if (priv->config == PIRQ_VIA_PCI)
27 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
29 pirq = readb((uintptr_t)priv->ibase + LINK_N2V(link, base));
33 /* IRQ# 0/1/2/8/13 are reserved */
34 if (pirq < 3 || pirq == 8 || pirq == 13)
37 return pirq == irq ? true : false;
40 int pirq_translate_link(struct udevice *dev, int link)
42 struct irq_router *priv = dev_get_priv(dev);
44 return LINK_V2N(link, priv->link_base);
47 void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
49 struct irq_router *priv = dev_get_priv(dev);
50 int base = priv->link_base;
52 /* IRQ# 0/1/2/8/13 are reserved */
53 if (irq < 3 || irq == 8 || irq == 13)
56 if (priv->config == PIRQ_VIA_PCI)
57 dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
59 writeb(irq, (uintptr_t)priv->ibase + LINK_N2V(link, base));
62 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
63 int entry_num, int bus, int device)
65 struct irq_info *slot = slot_base;
68 for (i = 0; i < entry_num; i++) {
69 if (slot->bus == bus && slot->devfn == (device << 3))
74 return (i == entry_num) ? NULL : slot;
77 static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
78 int bus, int device, int pin, int pirq)
81 slot->devfn = (device << 3) | 0;
82 slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
83 slot->irq[pin - 1].bitmap = priv->irq_mask;
86 static int create_pirq_routing_table(struct udevice *dev)
88 struct irq_router *priv = dev_get_priv(dev);
89 const void *blob = gd->fdt_blob;
93 struct irq_routing_table *rt;
94 struct irq_info *slot, *slot_base;
99 node = dev_of_offset(dev);
101 /* extract the bdf from fdt_pci_addr */
102 priv->bdf = dm_pci_get_bdf(dev->parent);
104 ret = fdt_stringlist_search(blob, node, "intel,pirq-config", "pci");
106 priv->config = PIRQ_VIA_PCI;
108 ret = fdt_stringlist_search(blob, node, "intel,pirq-config",
111 priv->config = PIRQ_VIA_IBASE;
116 ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
119 priv->link_base = ret;
121 priv->irq_mask = fdtdec_get_int(blob, node,
122 "intel,pirq-mask", PIRQ_BITMAP);
124 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
125 /* Reserve IRQ9 for SCI */
126 priv->irq_mask &= ~(1 << 9);
129 if (priv->config == PIRQ_VIA_IBASE) {
132 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
137 * Here we assume that the IBASE register has already been
138 * properly configured by U-Boot before.
140 * By 'valid' we mean:
141 * 1) a valid memory space carved within system memory space
142 * assigned to IBASE register block.
143 * 2) memory range decoding is enabled.
144 * Hence we don't do any santify test here.
146 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
150 priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
151 priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
153 cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
154 if (!cell || len % sizeof(struct pirq_routing))
156 count = len / sizeof(struct pirq_routing);
158 rt = calloc(1, sizeof(struct irq_routing_table));
162 /* Populate the PIRQ table fields */
163 rt->signature = PIRQ_SIGNATURE;
164 rt->version = PIRQ_VERSION;
165 rt->rtr_bus = PCI_BUS(priv->bdf);
166 rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
167 rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
168 rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
170 slot_base = rt->slots;
172 /* Now fill in the irq_info entries in the PIRQ table */
173 for (i = 0; i < count;
174 i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
175 struct pirq_routing pr;
177 pr.bdf = fdt_addr_to_cpu(cell[0]);
178 pr.pin = fdt_addr_to_cpu(cell[1]);
179 pr.pirq = fdt_addr_to_cpu(cell[2]);
181 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
182 i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
183 PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
186 slot = check_dup_entry(slot_base, irq_entries,
187 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
189 debug("found entry for bus %d device %d, ",
190 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
192 if (slot->irq[pr.pin - 1].link) {
196 * Sanity test on the routed PIRQ pin
198 * If they don't match, show a warning to tell
199 * there might be something wrong with the PIRQ
200 * routing information in the device tree.
202 if (slot->irq[pr.pin - 1].link !=
203 LINK_N2V(pr.pirq, priv->link_base))
204 debug("WARNING: Inconsistent PIRQ routing information\n");
208 slot = slot_base + irq_entries++;
210 debug("writing INT%c\n", 'A' + pr.pin - 1);
211 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
215 rt->size = irq_entries * sizeof(struct irq_info) + 32;
217 /* Fix up the table checksum */
218 rt->checksum = table_compute_checksum(rt, rt->size);
220 gd->arch.pirq_routing_table = rt;
225 static void irq_enable_sci(struct udevice *dev)
227 struct irq_router *priv = dev_get_priv(dev);
229 if (priv->actl_8bit) {
230 /* Bit7 must be turned on to enable ACPI */
231 dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
233 /* Write 0 to enable SCI on IRQ9 */
234 if (priv->config == PIRQ_VIA_PCI)
235 dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
237 writel(0, (uintptr_t)priv->ibase + priv->actl_addr);
241 int irq_router_common_init(struct udevice *dev)
245 ret = create_pirq_routing_table(dev);
247 debug("Failed to create pirq routing table\n");
251 pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
252 get_irq_slot_count(gd->arch.pirq_routing_table));
254 if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
260 int irq_router_probe(struct udevice *dev)
262 return irq_router_common_init(dev);
265 ulong write_pirq_routing_table(ulong addr)
267 if (!gd->arch.pirq_routing_table)
270 return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
273 static const struct udevice_id irq_router_ids[] = {
274 { .compatible = "intel,irq-router" },
278 U_BOOT_DRIVER(irq_router_drv) = {
281 .of_match = irq_router_ids,
282 .probe = irq_router_probe,
283 .priv_auto_alloc_size = sizeof(struct irq_router),
286 UCLASS_DRIVER(irq) = {