2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/pirq_routing.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static struct irq_router irq_router;
20 static struct irq_routing_table *pirq_routing_table;
22 bool pirq_check_irq_routed(int link, u8 irq)
25 int base = irq_router.link_base;
27 if (irq_router.config == PIRQ_VIA_PCI)
28 pirq = x86_pci_read_config8(irq_router.bdf,
29 LINK_N2V(link, base));
31 pirq = readb(irq_router.ibase + LINK_N2V(link, base));
35 /* IRQ# 0/1/2/8/13 are reserved */
36 if (pirq < 3 || pirq == 8 || pirq == 13)
39 return pirq == irq ? true : false;
42 int pirq_translate_link(int link)
44 return LINK_V2N(link, irq_router.link_base);
47 void pirq_assign_irq(int link, u8 irq)
49 int base = irq_router.link_base;
51 /* IRQ# 0/1/2/8/13 are reserved */
52 if (irq < 3 || irq == 8 || irq == 13)
55 if (irq_router.config == PIRQ_VIA_PCI)
56 x86_pci_write_config8(irq_router.bdf,
57 LINK_N2V(link, base), irq);
59 writeb(irq, irq_router.ibase + LINK_N2V(link, base));
62 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
63 int entry_num, int bus, int device)
65 struct irq_info *slot = slot_base;
68 for (i = 0; i < entry_num; i++) {
69 if (slot->bus == bus && slot->devfn == (device << 3))
74 return (i == entry_num) ? NULL : slot;
77 static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
81 slot->devfn = (device << 3) | 0;
82 slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
83 slot->irq[pin - 1].bitmap = irq_router.irq_mask;
86 __weak void cpu_irq_init(void)
91 static int create_pirq_routing_table(void)
93 const void *blob = gd->fdt_blob;
94 struct fdt_pci_addr addr;
98 struct irq_routing_table *rt;
99 struct irq_info *slot, *slot_base;
105 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_IRQ_ROUTER);
107 debug("%s: Cannot find irq router node\n", __func__);
111 /* TODO(sjg@chromium.org): Drop this when PIRQ is a driver */
112 parent = fdt_parent_offset(blob, node);
115 ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
120 /* extract the bdf from fdt_pci_addr */
121 irq_router.bdf = addr.phys_hi & 0xffff00;
123 ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
125 irq_router.config = PIRQ_VIA_PCI;
127 ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
129 irq_router.config = PIRQ_VIA_IBASE;
134 ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
137 irq_router.link_base = ret;
139 irq_router.irq_mask = fdtdec_get_int(blob, node,
140 "intel,pirq-mask", PIRQ_BITMAP);
142 if (irq_router.config == PIRQ_VIA_IBASE) {
145 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
150 * Here we assume that the IBASE register has already been
151 * properly configured by U-Boot before.
153 * By 'valid' we mean:
154 * 1) a valid memory space carved within system memory space
155 * assigned to IBASE register block.
156 * 2) memory range decoding is enabled.
157 * Hence we don't do any santify test here.
159 irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
161 irq_router.ibase &= ~0xf;
164 cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
165 if (!cell || len % sizeof(struct pirq_routing))
167 count = len / sizeof(struct pirq_routing);
169 rt = calloc(1, sizeof(struct irq_routing_table));
173 /* Populate the PIRQ table fields */
174 rt->signature = PIRQ_SIGNATURE;
175 rt->version = PIRQ_VERSION;
176 rt->rtr_bus = PCI_BUS(irq_router.bdf);
177 rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
178 PCI_FUNC(irq_router.bdf);
179 rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
180 rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
182 slot_base = rt->slots;
184 /* Now fill in the irq_info entries in the PIRQ table */
185 for (i = 0; i < count;
186 i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
187 struct pirq_routing pr;
189 pr.bdf = fdt_addr_to_cpu(cell[0]);
190 pr.pin = fdt_addr_to_cpu(cell[1]);
191 pr.pirq = fdt_addr_to_cpu(cell[2]);
193 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
194 i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
195 PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
198 slot = check_dup_entry(slot_base, irq_entries,
199 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
201 debug("found entry for bus %d device %d, ",
202 PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
204 if (slot->irq[pr.pin - 1].link) {
208 * Sanity test on the routed PIRQ pin
210 * If they don't match, show a warning to tell
211 * there might be something wrong with the PIRQ
212 * routing information in the device tree.
214 if (slot->irq[pr.pin - 1].link !=
215 LINK_N2V(pr.pirq, irq_router.link_base))
216 debug("WARNING: Inconsistent PIRQ routing information\n");
220 slot = slot_base + irq_entries++;
222 debug("writing INT%c\n", 'A' + pr.pin - 1);
223 fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
227 rt->size = irq_entries * sizeof(struct irq_info) + 32;
229 pirq_routing_table = rt;
238 return uclass_first_device(UCLASS_IRQ, &dev);
241 int irq_router_probe(struct udevice *dev)
247 ret = create_pirq_routing_table();
249 debug("Failed to create pirq routing table\n");
253 pirq_route_irqs(pirq_routing_table->slots,
254 get_irq_slot_count(pirq_routing_table));
259 u32 write_pirq_routing_table(u32 addr)
261 if (!pirq_routing_table)
264 return copy_pirq_routing_table(addr, pirq_routing_table);
267 static const struct udevice_id irq_router_ids[] = {
268 { .compatible = "intel,irq-router" },
272 U_BOOT_DRIVER(irq_router_drv) = {
275 .of_match = irq_router_ids,
276 .probe = irq_router_probe,
279 UCLASS_DRIVER(irq) = {