arch/x86/cpu/irq.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <asm/irq.h>
  14 #include <asm/pci.h>
  15 #include <asm/pirq_routing.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static struct irq_routing_table *pirq_routing_table;
  20
  21 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
  22 {
  23         struct irq_router *priv = dev_get_priv(dev);
  24         u8 pirq;
  25         int base = priv->link_base;
  26
  27         if (priv->config == PIRQ_VIA_PCI)
  28                 dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
  29         else
  30                 pirq = readb(priv->ibase + LINK_N2V(link, base));
  31
  32         pirq &= 0xf;
  33
  34         /* IRQ# 0/1/2/8/13 are reserved */
  35         if (pirq < 3 || pirq == 8 || pirq == 13)
  36                 return false;
  37
  38         return pirq == irq ? true : false;
  39 }
  40
  41 int pirq_translate_link(struct udevice *dev, int link)
  42 {
  43         struct irq_router *priv = dev_get_priv(dev);
  44
  45         return LINK_V2N(link, priv->link_base);
  46 }
  47
  48 void pirq_assign_irq(struct udevice *dev, int link, u8 irq)
  49 {
  50         struct irq_router *priv = dev_get_priv(dev);
  51         int base = priv->link_base;
  52
  53         /* IRQ# 0/1/2/8/13 are reserved */
  54         if (irq < 3 || irq == 8 || irq == 13)
  55                 return;
  56
  57         if (priv->config == PIRQ_VIA_PCI)
  58                 dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
  59         else
  60                 writeb(irq, priv->ibase + LINK_N2V(link, base));
  61 }
  62
  63 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
  64                                         int entry_num, int bus, int device)
  65 {
  66         struct irq_info *slot = slot_base;
  67         int i;
  68
  69         for (i = 0; i < entry_num; i++) {
  70                 if (slot->bus == bus && slot->devfn == (device << 3))
  71                         break;
  72                 slot++;
  73         }
  74
  75         return (i == entry_num) ? NULL : slot;
  76 }
  77
  78 static inline void fill_irq_info(struct irq_router *priv, struct irq_info *slot,
  79                                  int bus, int device, int pin, int pirq)
  80 {
  81         slot->bus = bus;
  82         slot->devfn = (device << 3) | 0;
  83         slot->irq[pin - 1].link = LINK_N2V(pirq, priv->link_base);
  84         slot->irq[pin - 1].bitmap = priv->irq_mask;
  85 }
  86
  87 static int create_pirq_routing_table(struct udevice *dev)
  88 {
  89         struct irq_router *priv = dev_get_priv(dev);
  90         const void *blob = gd->fdt_blob;
  91         int node;
  92         int len, count;
  93         const u32 *cell;
  94         struct irq_routing_table *rt;
  95         struct irq_info *slot, *slot_base;
  96         int irq_entries = 0;
  97         int i;
  98         int ret;
  99
 100         node = dev->of_offset;
 101
 102         /* extract the bdf from fdt_pci_addr */
 103         priv->bdf = dm_pci_get_bdf(dev->parent);
 104
 105         ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
 106         if (!ret) {
 107                 priv->config = PIRQ_VIA_PCI;
 108         } else {
 109                 ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
 110                 if (!ret)
 111                         priv->config = PIRQ_VIA_IBASE;
 112                 else
 113                         return -EINVAL;
 114         }
 115
 116         ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
 117         if (ret == -1)
 118                 return ret;
 119         priv->link_base = ret;
 120
 121         priv->irq_mask = fdtdec_get_int(blob, node,
 122                                         "intel,pirq-mask", PIRQ_BITMAP);
 123
 124         if (priv->config == PIRQ_VIA_IBASE) {
 125                 int ibase_off;
 126
 127                 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
 128                 if (!ibase_off)
 129                         return -EINVAL;
 130
 131                 /*
 132                  * Here we assume that the IBASE register has already been
 133                  * properly configured by U-Boot before.
 134                  *
 135                  * By 'valid' we mean:
 136                  *   1) a valid memory space carved within system memory space
 137                  *      assigned to IBASE register block.
 138                  *   2) memory range decoding is enabled.
 139                  * Hence we don't do any santify test here.
 140                  */
 141                 dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
 142                 priv->ibase &= ~0xf;
 143         }
 144
 145         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 146         if (!cell || len % sizeof(struct pirq_routing))
 147                 return -EINVAL;
 148         count = len / sizeof(struct pirq_routing);
 149
 150         rt = calloc(1, sizeof(struct irq_routing_table));
 151         if (!rt)
 152                 return -ENOMEM;
 153
 154         /* Populate the PIRQ table fields */
 155         rt->signature = PIRQ_SIGNATURE;
 156         rt->version = PIRQ_VERSION;
 157         rt->rtr_bus = PCI_BUS(priv->bdf);
 158         rt->rtr_devfn = (PCI_DEV(priv->bdf) << 3) | PCI_FUNC(priv->bdf);
 159         rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
 160         rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
 161
 162         slot_base = rt->slots;
 163
 164         /* Now fill in the irq_info entries in the PIRQ table */
 165         for (i = 0; i < count;
 166              i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
 167                 struct pirq_routing pr;
 168
 169                 pr.bdf = fdt_addr_to_cpu(cell[0]);
 170                 pr.pin = fdt_addr_to_cpu(cell[1]);
 171                 pr.pirq = fdt_addr_to_cpu(cell[2]);
 172
 173                 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
 174                       i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 175                       PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
 176                       'A' + pr.pirq);
 177
 178                 slot = check_dup_entry(slot_base, irq_entries,
 179                                        PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 180                 if (slot) {
 181                         debug("found entry for bus %d device %d, ",
 182                               PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 183
 184                         if (slot->irq[pr.pin - 1].link) {
 185                                 debug("skipping\n");
 186
 187                                 /*
 188                                  * Sanity test on the routed PIRQ pin
 189                                  *
 190                                  * If they don't match, show a warning to tell
 191                                  * there might be something wrong with the PIRQ
 192                                  * routing information in the device tree.
 193                                  */
 194                                 if (slot->irq[pr.pin - 1].link !=
 195                                         LINK_N2V(pr.pirq, priv->link_base))
 196                                         debug("WARNING: Inconsistent PIRQ routing information\n");
 197                                 continue;
 198                         }
 199                 } else {
 200                         slot = slot_base + irq_entries++;
 201                 }
 202                 debug("writing INT%c\n", 'A' + pr.pin - 1);
 203                 fill_irq_info(priv, slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 204                               pr.pin, pr.pirq);
 205         }
 206
 207         rt->size = irq_entries * sizeof(struct irq_info) + 32;
 208
 209         pirq_routing_table = rt;
 210
 211         return 0;
 212 }
 213
 214 int irq_router_common_init(struct udevice *dev)
 215 {
 216         int ret;
 217
 218         ret = create_pirq_routing_table(dev);
 219         if (ret) {
 220                 debug("Failed to create pirq routing table\n");
 221                 return ret;
 222         }
 223         /* Route PIRQ */
 224         pirq_route_irqs(dev, pirq_routing_table->slots,
 225                         get_irq_slot_count(pirq_routing_table));
 226
 227         return 0;
 228 }
 229
 230 int irq_router_probe(struct udevice *dev)
 231 {
 232         return irq_router_common_init(dev);
 233 }
 234
 235 u32 write_pirq_routing_table(u32 addr)
 236 {
 237         if (!pirq_routing_table)
 238                 return addr;
 239
 240         return copy_pirq_routing_table(addr, pirq_routing_table);
 241 }
 242
 243 static const struct udevice_id irq_router_ids[] = {
 244         { .compatible = "intel,irq-router" },
 245         { }
 246 };
 247
 248 U_BOOT_DRIVER(irq_router_drv) = {
 249         .name           = "intel_irq",
 250         .id             = UCLASS_IRQ,
 251         .of_match       = irq_router_ids,
 252         .probe          = irq_router_probe,
 253         .priv_auto_alloc_size = sizeof(struct irq_router),
 254 };
 255
 256 UCLASS_DRIVER(irq) = {
 257         .id             = UCLASS_IRQ,
 258         .name           = "irq",
 259 };