arch/x86/cpu/irq.c

   1 /*
   2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <asm/irq.h>
  14 #include <asm/pci.h>
  15 #include <asm/pirq_routing.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static struct irq_router irq_router;
  20 static struct irq_routing_table *pirq_routing_table;
  21
  22 bool pirq_check_irq_routed(int link, u8 irq)
  23 {
  24         u8 pirq;
  25         int base = irq_router.link_base;
  26
  27         if (irq_router.config == PIRQ_VIA_PCI)
  28                 pirq = x86_pci_read_config8(irq_router.bdf,
  29                                             LINK_N2V(link, base));
  30         else
  31                 pirq = readb(irq_router.ibase + LINK_N2V(link, base));
  32
  33         pirq &= 0xf;
  34
  35         /* IRQ# 0/1/2/8/13 are reserved */
  36         if (pirq < 3 || pirq == 8 || pirq == 13)
  37                 return false;
  38
  39         return pirq == irq ? true : false;
  40 }
  41
  42 int pirq_translate_link(int link)
  43 {
  44         return LINK_V2N(link, irq_router.link_base);
  45 }
  46
  47 void pirq_assign_irq(int link, u8 irq)
  48 {
  49         int base = irq_router.link_base;
  50
  51         /* IRQ# 0/1/2/8/13 are reserved */
  52         if (irq < 3 || irq == 8 || irq == 13)
  53                 return;
  54
  55         if (irq_router.config == PIRQ_VIA_PCI)
  56                 x86_pci_write_config8(irq_router.bdf,
  57                                       LINK_N2V(link, base), irq);
  58         else
  59                 writeb(irq, irq_router.ibase + LINK_N2V(link, base));
  60 }
  61
  62 static struct irq_info *check_dup_entry(struct irq_info *slot_base,
  63                                         int entry_num, int bus, int device)
  64 {
  65         struct irq_info *slot = slot_base;
  66         int i;
  67
  68         for (i = 0; i < entry_num; i++) {
  69                 if (slot->bus == bus && slot->devfn == (device << 3))
  70                         break;
  71                 slot++;
  72         }
  73
  74         return (i == entry_num) ? NULL : slot;
  75 }
  76
  77 static inline void fill_irq_info(struct irq_info *slot, int bus, int device,
  78                                  int pin, int pirq)
  79 {
  80         slot->bus = bus;
  81         slot->devfn = (device << 3) | 0;
  82         slot->irq[pin - 1].link = LINK_N2V(pirq, irq_router.link_base);
  83         slot->irq[pin - 1].bitmap = irq_router.irq_mask;
  84 }
  85
  86 static int create_pirq_routing_table(struct udevice *dev)
  87 {
  88         const void *blob = gd->fdt_blob;
  89         struct fdt_pci_addr addr;
  90         int node;
  91         int len, count;
  92         const u32 *cell;
  93         struct irq_routing_table *rt;
  94         struct irq_info *slot, *slot_base;
  95         int irq_entries = 0;
  96         int parent;
  97         int i;
  98         int ret;
  99
 100         node = dev->of_offset;
 101         parent = dev->parent->of_offset;
 102         ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
 103                                   "reg", &addr);
 104         if (ret)
 105                 return ret;
 106
 107         /* extract the bdf from fdt_pci_addr */
 108         irq_router.bdf = addr.phys_hi & 0xffff00;
 109
 110         ret = fdt_find_string(blob, node, "intel,pirq-config", "pci");
 111         if (!ret) {
 112                 irq_router.config = PIRQ_VIA_PCI;
 113         } else {
 114                 ret = fdt_find_string(blob, node, "intel,pirq-config", "ibase");
 115                 if (!ret)
 116                         irq_router.config = PIRQ_VIA_IBASE;
 117                 else
 118                         return -EINVAL;
 119         }
 120
 121         ret = fdtdec_get_int(blob, node, "intel,pirq-link", -1);
 122         if (ret == -1)
 123                 return ret;
 124         irq_router.link_base = ret;
 125
 126         irq_router.irq_mask = fdtdec_get_int(blob, node,
 127                                              "intel,pirq-mask", PIRQ_BITMAP);
 128
 129         if (irq_router.config == PIRQ_VIA_IBASE) {
 130                 int ibase_off;
 131
 132                 ibase_off = fdtdec_get_int(blob, node, "intel,ibase-offset", 0);
 133                 if (!ibase_off)
 134                         return -EINVAL;
 135
 136                 /*
 137                  * Here we assume that the IBASE register has already been
 138                  * properly configured by U-Boot before.
 139                  *
 140                  * By 'valid' we mean:
 141                  *   1) a valid memory space carved within system memory space
 142                  *      assigned to IBASE register block.
 143                  *   2) memory range decoding is enabled.
 144                  * Hence we don't do any santify test here.
 145                  */
 146                 irq_router.ibase = x86_pci_read_config32(irq_router.bdf,
 147                                                          ibase_off);
 148                 irq_router.ibase &= ~0xf;
 149         }
 150
 151         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 152         if (!cell || len % sizeof(struct pirq_routing))
 153                 return -EINVAL;
 154         count = len / sizeof(struct pirq_routing);
 155
 156         rt = calloc(1, sizeof(struct irq_routing_table));
 157         if (!rt)
 158                 return -ENOMEM;
 159
 160         /* Populate the PIRQ table fields */
 161         rt->signature = PIRQ_SIGNATURE;
 162         rt->version = PIRQ_VERSION;
 163         rt->rtr_bus = PCI_BUS(irq_router.bdf);
 164         rt->rtr_devfn = (PCI_DEV(irq_router.bdf) << 3) |
 165                         PCI_FUNC(irq_router.bdf);
 166         rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
 167         rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
 168
 169         slot_base = rt->slots;
 170
 171         /* Now fill in the irq_info entries in the PIRQ table */
 172         for (i = 0; i < count;
 173              i++, cell += sizeof(struct pirq_routing) / sizeof(u32)) {
 174                 struct pirq_routing pr;
 175
 176                 pr.bdf = fdt_addr_to_cpu(cell[0]);
 177                 pr.pin = fdt_addr_to_cpu(cell[1]);
 178                 pr.pirq = fdt_addr_to_cpu(cell[2]);
 179
 180                 debug("irq_info %d: b.d.f %x.%x.%x INT%c PIRQ%c\n",
 181                       i, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf),
 182                       PCI_FUNC(pr.bdf), 'A' + pr.pin - 1,
 183                       'A' + pr.pirq);
 184
 185                 slot = check_dup_entry(slot_base, irq_entries,
 186                                        PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 187                 if (slot) {
 188                         debug("found entry for bus %d device %d, ",
 189                               PCI_BUS(pr.bdf), PCI_DEV(pr.bdf));
 190
 191                         if (slot->irq[pr.pin - 1].link) {
 192                                 debug("skipping\n");
 193
 194                                 /*
 195                                  * Sanity test on the routed PIRQ pin
 196                                  *
 197                                  * If they don't match, show a warning to tell
 198                                  * there might be something wrong with the PIRQ
 199                                  * routing information in the device tree.
 200                                  */
 201                                 if (slot->irq[pr.pin - 1].link !=
 202                                         LINK_N2V(pr.pirq, irq_router.link_base))
 203                                         debug("WARNING: Inconsistent PIRQ routing information\n");
 204                                 continue;
 205                         }
 206                 } else {
 207                         slot = slot_base + irq_entries++;
 208                 }
 209                 debug("writing INT%c\n", 'A' + pr.pin - 1);
 210                 fill_irq_info(slot, PCI_BUS(pr.bdf), PCI_DEV(pr.bdf), pr.pin,
 211                               pr.pirq);
 212         }
 213
 214         rt->size = irq_entries * sizeof(struct irq_info) + 32;
 215
 216         pirq_routing_table = rt;
 217
 218         return 0;
 219 }
 220
 221 int irq_router_common_init(struct udevice *dev)
 222 {
 223         int ret;
 224
 225         ret = create_pirq_routing_table(dev);
 226         if (ret) {
 227                 debug("Failed to create pirq routing table\n");
 228                 return ret;
 229         }
 230         /* Route PIRQ */
 231         pirq_route_irqs(pirq_routing_table->slots,
 232                         get_irq_slot_count(pirq_routing_table));
 233
 234         return 0;
 235 }
 236
 237 int irq_router_probe(struct udevice *dev)
 238 {
 239         return irq_router_common_init(dev);
 240 }
 241
 242 u32 write_pirq_routing_table(u32 addr)
 243 {
 244         if (!pirq_routing_table)
 245                 return addr;
 246
 247         return copy_pirq_routing_table(addr, pirq_routing_table);
 248 }
 249
 250 static const struct udevice_id irq_router_ids[] = {
 251         { .compatible = "intel,irq-router" },
 252         { }
 253 };
 254
 255 U_BOOT_DRIVER(irq_router_drv) = {
 256         .name           = "intel_irq",
 257         .id             = UCLASS_IRQ,
 258         .of_match       = irq_router_ids,
 259         .probe          = irq_router_probe,
 260 };
 261
 262 UCLASS_DRIVER(irq) = {
 263         .id             = UCLASS_IRQ,
 264         .name           = "irq",
 265 };