1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
12 #include <asm/intel_regs.h>
14 #include <asm/lpc_common.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 /* Enable Prefetching and Caching */
19 static void enable_spi_prefetch(struct udevice *pch)
23 dm_pci_read_config8(pch, 0xdc, ®8);
25 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
26 dm_pci_write_config8(pch, 0xdc, reg8);
29 static void enable_port80_on_lpc(struct udevice *pch)
31 /* Enable port 80 POST on LPC */
32 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
33 clrbits_le32(RCB_REG(GCS), 4);
37 * lpc_early_init() - set up LPC serial ports and other early things
40 * @return 0 if OK, -ve on error
42 int lpc_common_early_init(struct udevice *dev)
44 struct udevice *pch = dev->parent;
52 count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
53 "intel,gen-dec", (u32 *)values,
54 sizeof(values) / sizeof(u32));
58 /* Set COM1/COM2 decode range */
59 dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010);
61 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
62 dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
63 GAMEL_LPC_EN | COMA_LPC_EN);
65 /* Write all registers but use 0 if we run out of data */
66 count = count * sizeof(u32) / sizeof(values[0]);
67 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
71 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
72 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
75 enable_spi_prefetch(pch);
77 /* This is already done in start.S, but let's do it in C */
78 enable_port80_on_lpc(pch);
83 int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect)
87 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
88 dm_pci_read_config8(dev, bios_ctrl, &bios_cntl);
90 bios_cntl &= ~BIOS_CTRL_BIOSWE;
93 bios_cntl |= BIOS_CTRL_BIOSWE;
96 dm_pci_write_config8(dev, bios_ctrl, bios_cntl);