1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
26 #include <asm/control_regs.h>
31 #include <asm/processor-flags.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 * Constructor for a conventional segment GDT (or LDT) entry
37 * This is a macro so it can be used in initialisers
39 #define GDT_ENTRY(flags, base, limit) \
40 ((((base) & 0xff000000ULL) << (56-24)) | \
41 (((flags) & 0x0000f0ffULL) << 40) | \
42 (((limit) & 0x000f0000ULL) << (48-16)) | \
43 (((base) & 0x00ffffffULL) << 16) | \
44 (((limit) & 0x0000ffffULL)))
51 struct cpu_device_id {
57 uint8_t x86; /* CPU family */
58 uint8_t x86_vendor; /* CPU vendor */
63 /* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
64 #ifndef CONFIG_TPL_BUILD
66 * List of cpu vendor strings along with their normalized
73 { X86_VENDOR_INTEL, "GenuineIntel", },
74 { X86_VENDOR_CYRIX, "CyrixInstead", },
75 { X86_VENDOR_AMD, "AuthenticAMD", },
76 { X86_VENDOR_UMC, "UMC UMC UMC ", },
77 { X86_VENDOR_NEXGEN, "NexGenDriven", },
78 { X86_VENDOR_CENTAUR, "CentaurHauls", },
79 { X86_VENDOR_RISE, "RiseRiseRise", },
80 { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
81 { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
82 { X86_VENDOR_NSC, "Geode by NSC", },
83 { X86_VENDOR_SIS, "SiS SiS SiS ", },
87 static void load_ds(u32 segment)
89 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
92 static void load_es(u32 segment)
94 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
97 static void load_fs(u32 segment)
99 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
102 static void load_gs(u32 segment)
104 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
107 static void load_ss(u32 segment)
109 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
112 static void load_gdt(const u64 *boot_gdt, u16 num_entries)
116 gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
117 gdt.ptr = (ulong)boot_gdt;
119 asm volatile("lgdtl %0\n" : : "m" (gdt));
122 void arch_setup_gd(gd_t *new_gd)
126 gdt_addr = new_gd->arch.gdt;
129 * CS: code, read/execute, 4 GB, base 0
131 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
133 gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
134 gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
136 /* DS: data, read/write, 4 GB, base 0 */
137 gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
140 * FS: data, read/write, sizeof (Global Data Pointer),
141 * base (Global Data Pointer)
143 new_gd->arch.gd_addr = new_gd;
144 gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093,
145 (ulong)&new_gd->arch.gd_addr,
146 sizeof(new_gd->arch.gd_addr) - 1);
148 /* 16-bit CS: code, read/execute, 64 kB, base 0 */
149 gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
151 /* 16-bit DS: data, read/write, 64 kB, base 0 */
152 gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
154 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
155 gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
157 load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
158 load_ds(X86_GDT_ENTRY_32BIT_DS);
159 load_es(X86_GDT_ENTRY_32BIT_DS);
160 load_gs(X86_GDT_ENTRY_32BIT_DS);
161 load_ss(X86_GDT_ENTRY_32BIT_DS);
162 load_fs(X86_GDT_ENTRY_32BIT_FS);
165 #ifdef CONFIG_HAVE_FSP
167 * Setup FSP execution environment GDT
169 * Per Intel FSP external architecture specification, before calling any FSP
170 * APIs, we need make sure the system is in flat 32-bit mode and both the code
171 * and data selectors should have full 4GB access range. Here we reuse the one
172 * we used in arch/x86/cpu/start16.S, and reload the segement registers.
174 void setup_fsp_gdt(void)
176 load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
177 load_ds(X86_GDT_ENTRY_32BIT_DS);
178 load_ss(X86_GDT_ENTRY_32BIT_DS);
179 load_es(X86_GDT_ENTRY_32BIT_DS);
180 load_fs(X86_GDT_ENTRY_32BIT_DS);
181 load_gs(X86_GDT_ENTRY_32BIT_DS);
186 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
187 * by the fact that they preserve the flags across the division of 5/2.
188 * PII and PPro exhibit this behavior too, but they have cpuid available.
192 * Perform the Cyrix 5/2 test. A Cyrix won't change
193 * the flags, while other 486 chips will.
195 static inline int test_cyrix_52div(void)
199 __asm__ __volatile__(
200 "sahf\n\t" /* clear flags (%eax = 0x0005) */
201 "div %b2\n\t" /* divide 5 by 2 */
202 "lahf" /* store flags into %ah */
207 /* AH is 0x02 on Cyrix after the divide.. */
208 return (unsigned char) (test >> 8) == 0x02;
211 #ifndef CONFIG_TPL_BUILD
213 * Detect a NexGen CPU running without BIOS hypercode new enough
214 * to have CPUID. (Thanks to Herbert Oppmann)
216 static int deep_magic_nexgen_probe(void)
220 __asm__ __volatile__ (
221 " movw $0x5555, %%ax\n"
229 : "=a" (ret) : : "cx", "dx");
234 static bool has_cpuid(void)
236 return flag_is_changeable_p(X86_EFLAGS_ID);
239 static bool has_mtrr(void)
241 return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
244 #ifndef CONFIG_TPL_BUILD
245 static int build_vendor_name(char *vendor_name)
247 struct cpuid_result result;
248 result = cpuid(0x00000000);
249 unsigned int *name_as_ints = (unsigned int *)vendor_name;
251 name_as_ints[0] = result.ebx;
252 name_as_ints[1] = result.edx;
253 name_as_ints[2] = result.ecx;
259 static void identify_cpu(struct cpu_device_id *cpu)
261 cpu->device = 0; /* fix gcc 4.4.4 warning */
264 * Do a quick and dirty check to save space - Intel and AMD only and
265 * just the vendor. This is enough for most TPL code.
267 if (spl_phase() == PHASE_TPL) {
268 struct cpuid_result result;
270 result = cpuid(0x00000000);
271 switch (result.ecx >> 24) {
272 case 'l': /* GenuineIntel */
273 cpu->vendor = X86_VENDOR_INTEL;
275 case 'D': /* AuthenticAMD */
276 cpu->vendor = X86_VENDOR_AMD;
279 cpu->vendor = X86_VENDOR_ANY;
285 /* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
286 #ifndef CONFIG_TPL_BUILD
287 char vendor_name[16];
290 vendor_name[0] = '\0'; /* Unset */
292 /* Find the id and vendor_name */
294 /* Its a 486 if we can modify the AC flag */
295 if (flag_is_changeable_p(X86_EFLAGS_AC))
296 cpu->device = 0x00000400; /* 486 */
298 cpu->device = 0x00000300; /* 386 */
299 if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
300 memcpy(vendor_name, "CyrixInstead", 13);
301 /* If we ever care we can enable cpuid here */
303 /* Detect NexGen with old hypercode */
304 else if (deep_magic_nexgen_probe())
305 memcpy(vendor_name, "NexGenDriven", 13);
309 cpuid_level = build_vendor_name(vendor_name);
310 vendor_name[12] = '\0';
312 /* Intel-defined flags: level 0x00000001 */
313 if (cpuid_level >= 0x00000001) {
314 cpu->device = cpuid_eax(0x00000001);
316 /* Have CPUID level 0 only unheard of */
317 cpu->device = 0x00000400;
320 cpu->vendor = X86_VENDOR_UNKNOWN;
321 for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
322 if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
323 cpu->vendor = x86_vendors[i].vendor;
330 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
332 c->x86 = (tfms >> 8) & 0xf;
333 c->x86_model = (tfms >> 4) & 0xf;
334 c->x86_mask = tfms & 0xf;
336 c->x86 += (tfms >> 20) & 0xff;
338 c->x86_model += ((tfms >> 16) & 0xF) << 4;
341 u32 cpu_get_family_model(void)
343 return gd->arch.x86_device & 0x0fff0ff0;
346 u32 cpu_get_stepping(void)
348 return gd->arch.x86_mask;
351 /* initialise FPU, reset EM, set MP and NE */
352 static void setup_cpu_features(void)
354 const u32 em_rst = ~X86_CR0_EM;
355 const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
358 "movl %%cr0, %%eax\n" \
361 "movl %%eax, %%cr0\n" \
362 : : "i" (em_rst), "i" (mp_ne_set) : "eax");
365 static void setup_identity(void)
367 /* identify CPU via cpuid and store the decoded info into gd->arch */
369 struct cpu_device_id cpu;
370 struct cpuinfo_x86 c;
373 get_fms(&c, cpu.device);
374 gd->arch.x86 = c.x86;
375 gd->arch.x86_vendor = cpu.vendor;
376 gd->arch.x86_model = c.x86_model;
377 gd->arch.x86_mask = c.x86_mask;
378 gd->arch.x86_device = cpu.device;
380 gd->arch.has_mtrr = has_mtrr();
384 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
385 static void setup_pci_ram_top(void)
387 gd->pci_ram_top = 0x80000000U;
390 static void setup_mtrr(void)
394 /* Configure fixed range MTRRs for some legacy regions */
395 if (!gd->arch.has_mtrr)
398 mtrr_cap = native_read_msr(MTRR_CAP_MSR);
399 if (mtrr_cap & MTRR_CAP_FIX) {
400 /* Mark the VGA RAM area as uncacheable */
401 native_write_msr(MTRR_FIX_16K_A0000_MSR,
402 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
403 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
406 * Mark the PCI ROM area as cacheable to improve ROM
407 * execution performance.
409 native_write_msr(MTRR_FIX_4K_C0000_MSR,
410 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
411 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
412 native_write_msr(MTRR_FIX_4K_C8000_MSR,
413 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
414 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
415 native_write_msr(MTRR_FIX_4K_D0000_MSR,
416 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
417 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
418 native_write_msr(MTRR_FIX_4K_D8000_MSR,
419 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
420 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
422 /* Enable the fixed range MTRRs */
423 msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
427 int x86_cpu_init_tpl(void)
429 setup_cpu_features();
435 int x86_cpu_init_f(void)
438 setup_cpu_features();
443 /* Set up the i8254 timer if required */
444 if (IS_ENABLED(CONFIG_I8254_TIMER))
450 int x86_cpu_reinit_f(void)
458 void x86_enable_caches(void)
463 cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
467 void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
469 void x86_disable_caches(void)
474 cr0 |= X86_CR0_NW | X86_CR0_CD;
479 void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
481 int dcache_status(void)
483 return !(read_cr0() & X86_CR0_CD);
486 void cpu_enable_paging_pae(ulong cr3)
488 __asm__ __volatile__(
489 /* Load the page table address */
492 "movl %%cr4, %%eax\n"
493 "orl $0x00000020, %%eax\n"
494 "movl %%eax, %%cr4\n"
496 "movl %%cr0, %%eax\n"
497 "orl $0x80000000, %%eax\n"
498 "movl %%eax, %%cr0\n"
504 void cpu_disable_paging_pae(void)
506 /* Turn off paging */
507 __asm__ __volatile__ (
509 "movl %%cr0, %%eax\n"
510 "andl $0x7fffffff, %%eax\n"
511 "movl %%eax, %%cr0\n"
513 "movl %%cr4, %%eax\n"
514 "andl $0xffffffdf, %%eax\n"
515 "movl %%eax, %%cr4\n"
521 static bool can_detect_long_mode(void)
523 return cpuid_eax(0x80000000) > 0x80000000UL;
526 static bool has_long_mode(void)
528 return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
531 int cpu_has_64bit(void)
533 return has_cpuid() && can_detect_long_mode() &&
537 #define PAGETABLE_BASE 0x80000
538 #define PAGETABLE_SIZE (6 * 4096)
541 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
543 * @pgtable: Pointer to a 24iKB block of memory
545 static void build_pagetable(uint32_t *pgtable)
549 memset(pgtable, '\0', PAGETABLE_SIZE);
551 /* Level 4 needs a single entry */
552 pgtable[0] = (ulong)&pgtable[1024] + 7;
554 /* Level 3 has one 64-bit entry for each GiB of memory */
555 for (i = 0; i < 4; i++)
556 pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
558 /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
559 for (i = 0; i < 2048; i++)
560 pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
563 int cpu_jump_to_64bit(ulong setup_base, ulong target)
567 pgtable = memalign(4096, PAGETABLE_SIZE);
571 build_pagetable(pgtable);
572 cpu_call64((ulong)pgtable, setup_base, target);
579 * Jump from SPL to U-Boot
581 * This function is work-in-progress with many issues to resolve.
583 * It works by setting up several regions:
584 * ptr - a place to put the code that jumps into 64-bit mode
585 * gdt - a place to put the global descriptor table
586 * pgtable - a place to put the page tables
588 * The cpu_call64() code is copied from ROM and then manually patched so that
589 * it has the correct GDT address in RAM. U-Boot is copied from ROM into
590 * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
591 * which changes to 64-bit mode and starts U-Boot.
593 int cpu_jump_to_64bit_uboot(ulong target)
595 typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
600 pgtable = (uint32_t *)PAGETABLE_BASE;
602 build_pagetable(pgtable);
604 extern long call64_stub_size;
605 ptr = malloc(call64_stub_size);
607 printf("Failed to allocate the cpu_call64 stub\n");
610 memcpy(ptr, cpu_call64, call64_stub_size);
615 * Copy U-Boot from ROM
616 * TODO(sjg@chromium.org): Figure out a way to get the text base
617 * correctly here, and in the device-tree binman definition.
619 * Also consider using FIT so we get the correct image length and
622 memcpy((char *)target, (char *)0xfff00000, 0x100000);
625 func((ulong)pgtable, 0, (ulong)target);
631 static int enable_smis(struct udevice *cpu, void *unused)
636 static struct mp_flight_record mp_steps[] = {
637 MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
638 /* Wait for APs to finish initialization before proceeding */
639 MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
642 int x86_mp_init(void)
644 struct mp_params mp_params;
646 mp_params.parallel_microcode_load = 0,
647 mp_params.flight_plan = &mp_steps[0];
648 mp_params.num_records = ARRAY_SIZE(mp_steps);
649 mp_params.microcode_pointer = 0;
651 if (mp_init(&mp_params)) {
652 printf("Warning: MP init failure\n");