1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
30 #include <asm/acpi_table.h>
31 #include <asm/control_regs.h>
32 #include <asm/coreboot_tables.h>
34 #include <asm/lapic.h>
35 #include <asm/microcode.h>
37 #include <asm/mrccache.h>
41 #include <asm/processor.h>
42 #include <asm/processor-flags.h>
43 #include <asm/interrupt.h>
44 #include <asm/tables.h>
45 #include <linux/compiler.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 #ifndef CONFIG_TPL_BUILD
50 static const char *const x86_vendor_name[] = {
51 [X86_VENDOR_INTEL] = "Intel",
52 [X86_VENDOR_CYRIX] = "Cyrix",
53 [X86_VENDOR_AMD] = "AMD",
54 [X86_VENDOR_UMC] = "UMC",
55 [X86_VENDOR_NEXGEN] = "NexGen",
56 [X86_VENDOR_CENTAUR] = "Centaur",
57 [X86_VENDOR_RISE] = "Rise",
58 [X86_VENDOR_TRANSMETA] = "Transmeta",
59 [X86_VENDOR_NSC] = "NSC",
60 [X86_VENDOR_SIS] = "SiS",
64 int __weak x86_cleanup_before_linux(void)
66 #ifdef CONFIG_BOOTSTAGE_STASH
67 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
68 CONFIG_BOOTSTAGE_STASH_SIZE);
74 int x86_init_cache(void)
80 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
82 void flush_cache(unsigned long dummy1, unsigned long dummy2)
87 /* Define these functions to allow ehch-hcd to function */
88 void flush_dcache_range(unsigned long start, unsigned long stop)
92 void invalidate_dcache_range(unsigned long start, unsigned long stop)
96 void dcache_enable(void)
101 void dcache_disable(void)
106 void icache_enable(void)
110 void icache_disable(void)
114 int icache_status(void)
119 #ifndef CONFIG_TPL_BUILD
120 const char *cpu_vendor_name(int vendor)
123 name = "<invalid cpu vendor>";
124 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
125 x86_vendor_name[vendor])
126 name = x86_vendor_name[vendor];
132 char *cpu_get_name(char *name)
134 unsigned int *name_as_ints = (unsigned int *)name;
135 struct cpuid_result regs;
139 /* This bit adds up to 48 bytes */
140 for (i = 0; i < 3; i++) {
141 regs = cpuid(0x80000002 + i);
142 name_as_ints[i * 4 + 0] = regs.eax;
143 name_as_ints[i * 4 + 1] = regs.ebx;
144 name_as_ints[i * 4 + 2] = regs.ecx;
145 name_as_ints[i * 4 + 3] = regs.edx;
147 name[CPU_MAX_NAME_LEN - 1] = '\0';
149 /* Skip leading spaces. */
157 int default_print_cpuinfo(void)
159 printf("CPU: %s, vendor %s, device %xh\n",
160 cpu_has_64bit() ? "x86_64" : "x86",
161 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
163 #ifdef CONFIG_HAVE_ACPI_RESUME
164 debug("ACPI previous sleep state: %s\n",
165 acpi_ss_string(gd->arch.prev_sleep_state));
171 void show_boot_progress(int val)
173 outb(val, POST_PORT);
176 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
178 * Implement a weak default function for boards that optionally
179 * need to clean up the system before jumping to the kernel.
181 __weak void board_final_cleanup(void)
185 int last_stage_init(void)
187 struct acpi_fadt __maybe_unused *fadt;
189 board_final_cleanup();
191 #ifdef CONFIG_HAVE_ACPI_RESUME
192 fadt = acpi_find_fadt();
194 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
200 #ifdef CONFIG_GENERATE_ACPI_TABLE
201 fadt = acpi_find_fadt();
203 /* Don't touch ACPI hardware on HW reduced platforms */
204 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
206 * Other than waiting for OSPM to request us to switch to ACPI
207 * mode, do it by ourselves, since SMI will not be triggered.
209 enter_acpi_mode(fadt->pm1a_cnt_blk);
217 static int x86_init_cpus(void)
220 debug("Init additional CPUs\n");
226 * This causes the cpu-x86 driver to be probed.
227 * We don't check return value here as we want to allow boards
228 * which have not been converted to use cpu uclass driver to boot.
230 uclass_first_device(UCLASS_CPU, &dev);
244 ret = x86_init_cpus();
249 * Set up the northbridge, PCH and LPC if available. Note that these
250 * may have had some limited pre-relocation init if they were probed
251 * before relocation, but this is post relocation.
253 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
254 uclass_first_device(UCLASS_PCH, &dev);
255 uclass_first_device(UCLASS_LPC, &dev);
257 /* Set up pin control if available */
258 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
259 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
264 #ifndef CONFIG_EFI_STUB
265 int reserve_arch(void)
267 #ifdef CONFIG_ENABLE_MRC_CACHE
271 #ifdef CONFIG_SEABIOS
272 high_table_reserve();
275 #ifdef CONFIG_HAVE_ACPI_RESUME
278 #ifdef CONFIG_HAVE_FSP
280 * Save stack address to CMOS so that at next S3 boot,
281 * we can use it as the stack address for fsp_contiue()
284 #endif /* CONFIG_HAVE_FSP */
285 #endif /* CONFIG_HAVE_ACPI_RESUME */