2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Alex Zuepke <azu@sysgo.de>
16 * Part of this file is adapted from coreboot
17 * src/arch/x86/lib/cpu.c
19 * SPDX-License-Identifier: GPL-2.0+
28 #include <asm/acpi_s3.h>
29 #include <asm/acpi_table.h>
30 #include <asm/control_regs.h>
31 #include <asm/coreboot_tables.h>
33 #include <asm/lapic.h>
34 #include <asm/microcode.h>
36 #include <asm/mrccache.h>
40 #include <asm/processor.h>
41 #include <asm/processor-flags.h>
42 #include <asm/interrupt.h>
43 #include <asm/tables.h>
44 #include <linux/compiler.h>
46 DECLARE_GLOBAL_DATA_PTR;
48 static const char *const x86_vendor_name[] = {
49 [X86_VENDOR_INTEL] = "Intel",
50 [X86_VENDOR_CYRIX] = "Cyrix",
51 [X86_VENDOR_AMD] = "AMD",
52 [X86_VENDOR_UMC] = "UMC",
53 [X86_VENDOR_NEXGEN] = "NexGen",
54 [X86_VENDOR_CENTAUR] = "Centaur",
55 [X86_VENDOR_RISE] = "Rise",
56 [X86_VENDOR_TRANSMETA] = "Transmeta",
57 [X86_VENDOR_NSC] = "NSC",
58 [X86_VENDOR_SIS] = "SiS",
61 int __weak x86_cleanup_before_linux(void)
63 #ifdef CONFIG_BOOTSTAGE_STASH
64 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
65 CONFIG_BOOTSTAGE_STASH_SIZE);
71 int x86_init_cache(void)
77 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
79 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
81 printf("resetting ...\n");
92 void flush_cache(unsigned long dummy1, unsigned long dummy2)
97 __weak void reset_cpu(ulong addr)
99 /* Do a hard reset through the chipset's reset control register */
100 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
105 void x86_full_reset(void)
107 outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
110 /* Define these functions to allow ehch-hcd to function */
111 void flush_dcache_range(unsigned long start, unsigned long stop)
115 void invalidate_dcache_range(unsigned long start, unsigned long stop)
119 void dcache_enable(void)
124 void dcache_disable(void)
129 void icache_enable(void)
133 void icache_disable(void)
137 int icache_status(void)
142 const char *cpu_vendor_name(int vendor)
145 name = "<invalid cpu vendor>";
146 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
147 x86_vendor_name[vendor])
148 name = x86_vendor_name[vendor];
153 char *cpu_get_name(char *name)
155 unsigned int *name_as_ints = (unsigned int *)name;
156 struct cpuid_result regs;
160 /* This bit adds up to 48 bytes */
161 for (i = 0; i < 3; i++) {
162 regs = cpuid(0x80000002 + i);
163 name_as_ints[i * 4 + 0] = regs.eax;
164 name_as_ints[i * 4 + 1] = regs.ebx;
165 name_as_ints[i * 4 + 2] = regs.ecx;
166 name_as_ints[i * 4 + 3] = regs.edx;
168 name[CPU_MAX_NAME_LEN - 1] = '\0';
170 /* Skip leading spaces. */
178 int default_print_cpuinfo(void)
180 printf("CPU: %s, vendor %s, device %xh\n",
181 cpu_has_64bit() ? "x86_64" : "x86",
182 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
184 #ifdef CONFIG_HAVE_ACPI_RESUME
185 debug("ACPI previous sleep state: %s\n",
186 acpi_ss_string(gd->arch.prev_sleep_state));
192 void show_boot_progress(int val)
194 outb(val, POST_PORT);
197 #ifndef CONFIG_SYS_COREBOOT
199 * Implement a weak default function for boards that optionally
200 * need to clean up the system before jumping to the kernel.
202 __weak void board_final_cleanup(void)
206 int last_stage_init(void)
208 board_final_cleanup();
210 #if CONFIG_HAVE_ACPI_RESUME
211 struct acpi_fadt *fadt = acpi_find_fadt();
213 if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3)
223 static int x86_init_cpus(void)
226 debug("Init additional CPUs\n");
232 * This causes the cpu-x86 driver to be probed.
233 * We don't check return value here as we want to allow boards
234 * which have not been converted to use cpu uclass driver to boot.
236 uclass_first_device(UCLASS_CPU, &dev);
250 ret = x86_init_cpus();
255 * Set up the northbridge, PCH and LPC if available. Note that these
256 * may have had some limited pre-relocation init if they were probed
257 * before relocation, but this is post relocation.
259 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
260 uclass_first_device(UCLASS_PCH, &dev);
261 uclass_first_device(UCLASS_LPC, &dev);
263 /* Set up pin control if available */
264 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
265 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
270 #ifndef CONFIG_EFI_STUB
271 int reserve_arch(void)
273 #ifdef CONFIG_ENABLE_MRC_CACHE
277 #ifdef CONFIG_SEABIOS
278 high_table_reserve();
281 #ifdef CONFIG_HAVE_ACPI_RESUME
284 #ifdef CONFIG_HAVE_FSP
286 * Save stack address to CMOS so that at next S3 boot,
287 * we can use it as the stack address for fsp_contiue()
290 #endif /* CONFIG_HAVE_FSP */
291 #endif /* CONFIG_HAVE_ACPI_RESUME */