1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * Graeme Russ, graeme.russ@gmail.com.
15 #include <asm/arch/sysinfo.h>
16 #include <asm/arch/timestamp.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 int arch_cpu_init(void)
22 int ret = get_coreboot_info(&lib_sysinfo);
24 printf("Failed to parse coreboot tables.\n");
30 return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
39 int print_cpuinfo(void)
41 return default_print_cpuinfo();
44 static void board_final_cleanup(void)
47 * Un-cache the ROM so the kernel has one
48 * more MTRR available.
50 * Coreboot should have assigned this to the
51 * top available variable MTRR.
53 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
54 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
56 /* Make sure this MTRR is the correct Write-Protected type */
57 if (top_type == MTRR_TYPE_WRPROT) {
58 struct mtrr_state state;
60 mtrr_open(&state, true);
61 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
62 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
63 mtrr_close(&state, true);
66 if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
68 * Issue SMI to coreboot to lock down ME and registers
69 * when allowed via device tree
71 printf("Finalizing coreboot\n");
76 int last_stage_init(void)
78 /* start usb so that usb keyboard can be used as input device */
79 if (CONFIG_IS_ENABLED(USB_KEYBOARD))
82 board_final_cleanup();