845f86a1766c15afd9da5c0630978dcd3930b40d
[oweals/u-boot.git] / arch / x86 / cpu / coreboot / coreboot.c
1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  * (C) Copyright 2008
4  * Graeme Russ, graeme.russ@gmail.com.
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #include <common.h>
10 #include <fdtdec.h>
11 #include <asm/io.h>
12 #include <asm/msr.h>
13 #include <asm/mtrr.h>
14 #include <asm/arch/sysinfo.h>
15 #include <asm/arch/timestamp.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 int arch_cpu_init(void)
20 {
21         int ret = get_coreboot_info(&lib_sysinfo);
22         if (ret != 0) {
23                 printf("Failed to parse coreboot tables.\n");
24                 return ret;
25         }
26
27         timestamp_init();
28
29         return x86_cpu_init_f();
30 }
31
32 int board_early_init_f(void)
33 {
34         return 0;
35 }
36
37 int print_cpuinfo(void)
38 {
39         return default_print_cpuinfo();
40 }
41
42 int last_stage_init(void)
43 {
44         if (gd->flags & GD_FLG_COLD_BOOT)
45                 timestamp_add_to_bootstage();
46
47         return 0;
48 }
49
50 void board_final_cleanup(void)
51 {
52         /*
53          * Un-cache the ROM so the kernel has one
54          * more MTRR available.
55          *
56          * Coreboot should have assigned this to the
57          * top available variable MTRR.
58          */
59         u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
60         u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
61
62         /* Make sure this MTRR is the correct Write-Protected type */
63         if (top_type == MTRR_TYPE_WRPROT) {
64                 struct mtrr_state state;
65
66                 mtrr_open(&state);
67                 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
68                 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
69                 mtrr_close(&state);
70         }
71
72         if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
73                 /*
74                  * Issue SMI to coreboot to lock down ME and registers
75                  * when allowed via device tree
76                  */
77                 printf("Finalizing coreboot\n");
78                 outb(0xcb, 0xb2);
79         }
80 }
81
82 int misc_init_r(void)
83 {
84         return 0;
85 }
86
87 int arch_misc_init(void)
88 {
89         return 0;
90 }