arch/x86/cpu/coreboot/coreboot.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  * (C) Copyright 2008
   5  * Graeme Russ, graeme.russ@gmail.com.
   6  */
   7
   8 #include <common.h>
   9 #include <fdtdec.h>
  10 #include <asm/io.h>
  11 #include <asm/msr.h>
  12 #include <asm/mtrr.h>
  13 #include <asm/arch/sysinfo.h>
  14 #include <asm/arch/timestamp.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 int arch_cpu_init(void)
  19 {
  20         int ret = get_coreboot_info(&lib_sysinfo);
  21         if (ret != 0) {
  22                 printf("Failed to parse coreboot tables.\n");
  23                 return ret;
  24         }
  25
  26         timestamp_init();
  27
  28         return x86_cpu_init_f();
  29 }
  30
  31 int checkcpu(void)
  32 {
  33         return 0;
  34 }
  35
  36 int print_cpuinfo(void)
  37 {
  38         return default_print_cpuinfo();
  39 }
  40
  41 static void board_final_cleanup(void)
  42 {
  43         /*
  44          * Un-cache the ROM so the kernel has one
  45          * more MTRR available.
  46          *
  47          * Coreboot should have assigned this to the
  48          * top available variable MTRR.
  49          */
  50         u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
  51         u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
  52
  53         /* Make sure this MTRR is the correct Write-Protected type */
  54         if (top_type == MTRR_TYPE_WRPROT) {
  55                 struct mtrr_state state;
  56
  57                 mtrr_open(&state);
  58                 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
  59                 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
  60                 mtrr_close(&state);
  61         }
  62
  63         if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
  64                 /*
  65                  * Issue SMI to coreboot to lock down ME and registers
  66                  * when allowed via device tree
  67                  */
  68                 printf("Finalizing coreboot\n");
  69                 outb(0xcb, 0xb2);
  70         }
  71 }
  72
  73 int last_stage_init(void)
  74 {
  75         if (gd->flags & GD_FLG_COLD_BOOT)
  76                 timestamp_add_to_bootstage();
  77
  78         board_final_cleanup();
  79
  80         return 0;
  81 }
  82
  83 int misc_init_r(void)
  84 {
  85         return 0;
  86 }