2 * Copyright (c) 2011 The Chromium OS Authors.
4 * Graeme Russ, graeme.russ@gmail.com.
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/u-boot-x86.h>
15 #include <asm/cache.h>
19 #include <asm/arch/tables.h>
20 #include <asm/arch/sysinfo.h>
21 #include <asm/arch/timestamp.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 int arch_cpu_init(void)
27 int ret = get_coreboot_info(&lib_sysinfo);
29 printf("Failed to parse coreboot tables.\n");
35 return x86_cpu_init_f();
38 int board_early_init_f(void)
43 int print_cpuinfo(void)
45 return default_print_cpuinfo();
48 int last_stage_init(void)
50 if (gd->flags & GD_FLG_COLD_BOOT)
51 timestamp_add_to_bootstage();
56 #ifndef CONFIG_SYS_NO_FLASH
57 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
63 int board_eth_init(bd_t *bis)
65 return pci_eth_init(bis);
68 void board_final_cleanup(void)
70 /* Un-cache the ROM so the kernel has one
71 * more MTRR available.
73 * Coreboot should have assigned this to the
74 * top available variable MTRR.
76 u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
77 u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
79 /* Make sure this MTRR is the correct Write-Protected type */
80 if (top_type == MTRR_TYPE_WRPROT) {
81 struct mtrr_state state;
84 wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
85 wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
89 /* Issue SMI to Coreboot to lock down ME and registers */
90 printf("Finalizing Coreboot\n");
94 void panic_puts(const char *str)
96 NS16550_t port = (NS16550_t)0x3f8;
98 NS16550_init(port, 1);
100 NS16550_putc(port, *str++);
103 int misc_init_r(void)