1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
7 #include <asm/global_data.h>
8 #include <asm/msr-index.h>
9 #include <asm/processor-flags.h>
12 * rdi - 32-bit code segment selector
13 * rsi - target address
14 * rdx - table address (0 if none)
21 /* Save table pointer */
25 * Debugging option, this outputs characters to the console UART
32 push %rdi /* 32-bit code segment */
33 lea compat(%rip), %rax
35 .byte 0x48 /* REX prefix to force 64-bit far return */
40 * We are now in compatibility mode with a default operand size of
41 * 32 bits. First disable paging.
44 andl $~X86_CR0_PG, %eax
51 /* Disable Long mode in EFER (Extended Feature Enable Register) */
57 /* Set up table pointer for _x86boot_start */
60 /* Jump to the required target */
61 pushl %edi /* 32-bit code segment */
62 pushl %esi /* 32-bit target address */