1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
5 * From coreboot src/soc/intel/broadwell/romstage/raminit.c
16 #include <asm/lpc_common.h>
17 #include <asm/mrccache.h>
18 #include <asm/mrc_common.h>
21 #include <asm/arch/iomap.h>
22 #include <asm/arch/me.h>
23 #include <asm/arch/pch.h>
24 #include <asm/arch/pei_data.h>
25 #include <asm/arch/pm.h>
27 ulong board_get_usable_ram_top(ulong total_size)
29 return mrc_common_board_get_usable_ram_top(total_size);
32 int dram_init_banksize(void)
34 mrc_common_dram_init_banksize();
39 static unsigned long get_top_of_ram(struct udevice *dev)
42 * Base of DPR is top of usable DRAM below 4GiB. The register has
43 * 1 MiB alignment and reports the TOP of the range, the base
44 * must be calculated from the size in MiB in bits 11:4.
48 dm_pci_read_config32(dev, DPR, &dpr);
49 tom = dpr & ~((1 << 20) - 1);
51 debug("dpt %08x tom %08x\n", dpr, tom);
52 /* Subtract DMA Protected Range size if enabled */
54 tom -= (dpr & DPR_SIZE_MASK) << 16;
56 return (unsigned long)tom;
60 * sdram_find() - Find available memory
62 * This is a bit complicated since on x86 there are system memory holes all
63 * over the place. We create a list of available memory blocks
65 * @dev: Northbridge device
67 static int sdram_find(struct udevice *dev)
69 struct memory_info *info = &gd->arch.meminfo;
72 top_of_ram = get_top_of_ram(dev);
73 mrc_add_memory_area(info, 0, top_of_ram);
75 /* Add MTRRs for memory */
76 mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
81 static int prepare_mrc_cache(struct pei_data *pei_data)
83 struct mrc_data_container *mrc_cache;
84 struct mrc_region entry;
87 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
90 mrc_cache = mrccache_find_current(&entry);
94 pei_data->saved_data = mrc_cache->data;
95 pei_data->saved_data_size = mrc_cache->data_size;
96 debug("%s: at %p, size %x checksum %04x\n", __func__,
97 pei_data->saved_data, pei_data->saved_data_size,
105 struct pei_data _pei_data __aligned(8);
106 struct pei_data *pei_data = &_pei_data;
107 struct udevice *dev, *me_dev, *pch_dev;
108 struct chipset_power_state ps;
109 const void *spd_data;
112 memset(pei_data, '\0', sizeof(struct pei_data));
114 /* Print ME state before MRC */
115 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
117 debug("Cannot get ME (err=%d)\n", ret);
120 intel_me_status(me_dev);
122 /* Save ME HSIO version */
123 ret = uclass_first_device_err(UCLASS_PCH, &pch_dev);
125 debug("Cannot get PCH (err=%d)\n", ret);
128 power_state_get(pch_dev, &ps);
130 intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
132 broadwell_fill_pei_data(pei_data);
133 mainboard_fill_pei_data(pei_data);
135 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
137 debug("Cannot get Northbridge (err=%d)\n", ret);
141 ret = mrc_locate_spd(dev, size, &spd_data);
143 debug("Cannot locate SPD (err=%d)\n", ret);
146 memcpy(pei_data->spd_data[0][0], spd_data, size);
147 memcpy(pei_data->spd_data[1][0], spd_data, size);
149 ret = prepare_mrc_cache(pei_data);
151 debug("prepare_mrc_cache failed: %d\n", ret);
153 debug("PEI version %#x\n", pei_data->pei_version);
154 ret = mrc_common_init(dev, pei_data, true);
156 debug("mrc_common_init() failed(err=%d)\n", ret);
159 debug("Memory init done\n");
161 ret = sdram_find(dev);
163 debug("sdram_find() failed (err=%d)\n", ret);
166 gd->ram_size = gd->arch.meminfo.total_32bit_memory;
167 debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
169 debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
170 pei_data->data_to_save);
171 /* S3 resume: don't save scrambler seed or MRC data */
172 if (pei_data->boot_mode != SLEEP_STATE_S3) {
173 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
176 * This will be copied to SDRAM in reserve_arch(), then written
177 * to SPI flash in mrccache_save()
179 mrc->buf = (char *)pei_data->data_to_save;
180 mrc->len = pei_data->data_to_save_size;
182 gd->arch.pei_meminfo = pei_data->meminfo;
187 /* Use this hook to save our SDRAM parameters */
188 int misc_init_r(void)
192 ret = mrccache_save();
194 printf("Unable to save MRC data: %d\n", ret);
196 debug("Saved MRC cache data\n");
201 static const struct udevice_id broadwell_syscon_ids[] = {
202 { .compatible = "intel,me", .data = X86_SYSCON_ME },
206 U_BOOT_DRIVER(syscon_intel_me) = {
207 .name = "intel_me_syscon",
209 .of_match = broadwell_syscon_ids,