2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
6 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
13 #include <asm/cpu_x86.h>
14 #include <asm/cpu_common.h>
15 #include <asm/intel_regs.h>
18 #include <asm/turbo.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/pch.h>
21 #include <asm/arch/rcb.h>
23 struct cpu_broadwell_priv {
27 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
28 static const u8 power_limit_time_sec_to_msr[] = {
56 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
57 static const u8 power_limit_time_msr_to_sec[] = {
85 int arch_cpu_init_dm(void)
90 /* Start up the LPC so we have serial */
91 ret = uclass_first_device(UCLASS_LPC, &dev);
96 ret = cpu_set_flex_ratio_to_tdp_nominal();
103 void set_max_freq(void)
105 msr_t msr, perf_ctl, platform_info;
107 /* Check for configurable TDP option */
108 platform_info = msr_read(MSR_PLATFORM_INFO);
110 if ((platform_info.hi >> 1) & 3) {
111 /* Set to nominal TDP ratio */
112 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
113 perf_ctl.lo = (msr.lo & 0xff) << 8;
115 /* Platform Info bits 15:8 give max ratio */
116 msr = msr_read(MSR_PLATFORM_INFO);
117 perf_ctl.lo = msr.lo & 0xff00;
121 msr_write(IA32_PERF_CTL, perf_ctl);
123 debug("CPU: frequency set to %d MHz\n",
124 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
127 int arch_cpu_init(void)
129 post_code(POST_CPU_INIT);
131 return x86_cpu_init_f();
140 ret = cpu_common_init();
143 gd->arch.pei_boot_mode = PEI_BOOT_NONE;
148 int print_cpuinfo(void)
150 char processor_name[CPU_MAX_NAME_LEN];
153 /* Print processor name */
154 name = cpu_get_name(processor_name);
155 printf("CPU: %s\n", name);
161 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
162 * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
163 * when a core is woken up
165 static int pcode_ready(void)
168 const int delay_step = 10;
172 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
175 wait_count += delay_step;
177 } while (wait_count < 1000);
182 static u32 pcode_mailbox_read(u32 command)
188 debug("PCODE: mailbox timeout on wait ready\n");
192 /* Send command and start transaction */
193 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
197 debug("PCODE: mailbox timeout on completion\n");
202 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
205 static int pcode_mailbox_write(u32 command, u32 data)
211 debug("PCODE: mailbox timeout on wait ready\n");
215 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
217 /* Send command and start transaction */
218 writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
222 debug("PCODE: mailbox timeout on completion\n");
229 /* @dev is the CPU device */
230 static void initialize_vr_config(struct udevice *dev)
235 debug("Initializing VR config\n");
237 /* Configure VR_CURRENT_CONFIG */
238 msr = msr_read(MSR_VR_CURRENT_CONFIG);
240 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
243 msr.hi &= 0xc0000000;
244 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
245 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
246 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
247 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
248 /* Leave the max instantaneous current limit (12:0) to default */
249 msr_write(MSR_VR_CURRENT_CONFIG, msr);
251 /* Configure VR_MISC_CONFIG MSR */
252 msr = msr_read(MSR_VR_MISC_CONFIG);
253 /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
254 msr.hi &= ~(0x3ff << (40 - 32));
255 msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
256 /* Set IOUT_OFFSET to 0 */
258 /* Set entry ramp rate to slow */
259 msr.hi &= ~(1 << (51 - 32));
260 /* Enable decay mode on C-state entry */
261 msr.hi |= (1 << (52 - 32));
262 /* Set the slow ramp rate */
263 msr.hi &= ~(0x3 << (53 - 32));
264 /* Configure the C-state exit ramp rate */
265 ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
266 "intel,slow-ramp", -1);
268 /* Configured slow ramp rate */
269 msr.hi |= ((ramp & 0x3) << (53 - 32));
270 /* Set exit ramp rate to slow */
271 msr.hi &= ~(1 << (50 - 32));
273 /* Fast ramp rate / 4 */
274 msr.hi |= (0x01 << (53 - 32));
275 /* Set exit ramp rate to fast */
276 msr.hi |= (1 << (50 - 32));
278 /* Set MIN_VID (31:24) to allow CPU to have full control */
279 msr.lo &= ~0xff000000;
280 min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
282 msr.lo |= (min_vid & 0xff) << 24;
283 msr_write(MSR_VR_MISC_CONFIG, msr);
285 /* Configure VR_MISC_CONFIG2 MSR */
286 msr = msr_read(MSR_VR_MISC_CONFIG2);
289 * Allow CPU to control minimum voltage completely (15:8) and
290 * set the fast ramp voltage in 10mV steps
292 if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
293 msr.lo |= 0x006a; /* 1.56V */
295 msr.lo |= 0x006f; /* 1.60V */
296 msr_write(MSR_VR_MISC_CONFIG2, msr);
298 /* Set C9/C10 VCC Min */
299 pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
302 static int calibrate_24mhz_bclk(void)
311 /* A non-zero value initiates the PCODE calibration */
312 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
313 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
314 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
320 err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
322 debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
324 /* Read the calibrated value */
325 writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
326 MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
332 debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
333 readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
338 static void configure_pch_power_sharing(void)
340 u32 pch_power, pch_power_ext, pmsync, pmsync2;
343 /* Read PCH Power levels from PCODE */
344 pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
345 pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
347 debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
350 pmsync = readl(RCB_REG(PMSYNC_CONFIG));
351 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
354 * Program PMSYNC_TPR_CONFIG PCH power limit values
355 * pmsync[0:4] = mailbox[0:5]
356 * pmsync[8:12] = mailbox[6:11]
357 * pmsync[16:20] = mailbox[12:17]
359 for (i = 0; i < 3; i++) {
360 u32 level = pch_power & 0x3f;
362 pmsync &= ~(0x1f << (i * 8));
363 pmsync |= (level & 0x1f) << (i * 8);
365 writel(pmsync, RCB_REG(PMSYNC_CONFIG));
368 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
369 * pmsync2[0:4] = mailbox[23:18]
370 * pmsync2[8:12] = mailbox_ext[6:11]
371 * pmsync2[16:20] = mailbox_ext[12:17]
372 * pmsync2[24:28] = mailbox_ext[18:22]
375 pmsync2 |= pch_power & 0x1f;
377 for (i = 1; i < 4; i++) {
378 u32 level = pch_power_ext & 0x3f;
380 pmsync2 &= ~(0x1f << (i * 8));
381 pmsync2 |= (level & 0x1f) << (i * 8);
383 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
386 static int bsp_init_before_ap_bringup(struct udevice *dev)
390 initialize_vr_config(dev);
391 ret = calibrate_24mhz_bclk();
394 configure_pch_power_sharing();
399 int cpu_config_tdp_levels(void)
403 /* Bits 34:33 indicate how many levels supported */
404 platform_info = msr_read(MSR_PLATFORM_INFO);
405 return (platform_info.hi >> 1) & 3;
408 static void set_max_ratio(void)
414 /* Check for configurable TDP option */
415 if (turbo_get_state() == TURBO_ENABLED) {
416 msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
417 perf_ctl.lo = (msr.lo & 0xff) << 8;
418 } else if (cpu_config_tdp_levels()) {
419 /* Set to nominal TDP ratio */
420 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
421 perf_ctl.lo = (msr.lo & 0xff) << 8;
423 /* Platform Info bits 15:8 give max ratio */
424 msr = msr_read(MSR_PLATFORM_INFO);
425 perf_ctl.lo = msr.lo & 0xff00;
427 msr_write(IA32_PERF_CTL, perf_ctl);
429 debug("cpu: frequency set to %d\n",
430 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
433 int broadwell_init(struct udevice *dev)
435 struct cpu_broadwell_priv *priv = dev_get_priv(dev);
441 msr = msr_read(CORE_THREAD_COUNT_MSR);
442 num_threads = (msr.lo >> 0) & 0xffff;
443 num_cores = (msr.lo >> 16) & 0xffff;
444 debug("CPU has %u cores, %u threads enabled\n", num_cores,
447 priv->ht_disabled = num_threads == num_cores;
449 ret = bsp_init_before_ap_bringup(dev);
458 static void configure_mca(void)
461 const unsigned int mcg_cap_msr = 0x179;
465 msr = msr_read(mcg_cap_msr);
466 num_banks = msr.lo & 0xff;
470 * TODO(adurbin): This should only be done on a cold boot. Also, some
471 * of these banks are core vs package scope. For now every CPU clears
474 for (i = 0; i < num_banks; i++)
475 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
478 static void enable_lapic_tpr(void)
482 msr = msr_read(MSR_PIC_MSG_CONTROL);
483 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
484 msr_write(MSR_PIC_MSG_CONTROL, msr);
488 static void configure_c_states(void)
492 msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
493 msr.lo |= (1 << 31); /* Timed MWAIT Enable */
494 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
495 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
496 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
497 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
498 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
499 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
500 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
501 /* The deepest package c-state defaults to factory-configured value */
502 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
504 msr = msr_read(MSR_MISC_PWR_MGMT);
505 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
506 msr_write(MSR_MISC_PWR_MGMT, msr);
508 msr = msr_read(MSR_POWER_CTL);
509 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
510 msr.lo |= (1 << 1); /* C1E Enable */
511 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
512 msr_write(MSR_POWER_CTL, msr);
514 /* C-state Interrupt Response Latency Control 0 - package C3 latency */
516 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
517 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
519 /* C-state Interrupt Response Latency Control 1 */
521 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
522 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
524 /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
526 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
527 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
529 /* C-state Interrupt Response Latency Control 3 - package C8 */
531 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
532 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
534 /* C-state Interrupt Response Latency Control 4 - package C9 */
536 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
537 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
539 /* C-state Interrupt Response Latency Control 5 - package C10 */
541 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
542 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
545 static void configure_misc(void)
549 msr = msr_read(MSR_IA32_MISC_ENABLE);
550 msr.lo |= (1 << 0); /* Fast String enable */
551 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
552 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
553 msr_write(MSR_IA32_MISC_ENABLE, msr);
555 /* Disable thermal interrupts */
558 msr_write(MSR_IA32_THERM_INTERRUPT, msr);
560 /* Enable package critical interrupt only */
563 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
566 static void configure_thermal_target(struct udevice *dev)
571 tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
572 "intel,tcc-offset", 0);
574 /* Set TCC activaiton offset if supported */
575 msr = msr_read(MSR_PLATFORM_INFO);
576 if ((msr.lo & (1 << 30)) && tcc_offset) {
577 msr = msr_read(MSR_TEMPERATURE_TARGET);
578 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
579 msr.lo |= (tcc_offset & 0xf) << 24;
580 msr_write(MSR_TEMPERATURE_TARGET, msr);
584 static void configure_dca_cap(void)
586 struct cpuid_result cpuid_regs;
589 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
590 cpuid_regs = cpuid(1);
591 if (cpuid_regs.ecx & (1 << 18)) {
592 msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
594 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
598 static void set_energy_perf_bias(u8 policy)
603 /* Determine if energy efficient policy is supported */
604 ecx = cpuid_ecx(0x6);
605 if (!(ecx & (1 << 3)))
608 /* Energy Policy is bits 3:0 */
609 msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
611 msr.lo |= policy & 0xf;
612 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
614 debug("cpu: energy policy set to %u\n", policy);
617 /* All CPUs including BSP will run the following function */
618 static void cpu_core_init(struct udevice *dev)
620 /* Clear out pending MCEs */
623 /* Enable the local cpu apics */
626 /* Configure C States */
627 configure_c_states();
629 /* Configure Enhanced SpeedStep and Thermal Sensors */
632 /* Thermal throttle activation offset */
633 configure_thermal_target(dev);
635 /* Enable Direct Cache Access */
638 /* Set energy policy */
639 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
646 * Configure processor power limits if possible
647 * This must be done AFTER set of BIOS_RESET_CPL
649 void cpu_set_power_limits(int power_limit_1_time)
654 unsigned tdp, min_power, max_power, max_time;
655 u8 power_limit_1_val;
657 msr = msr_read(MSR_PLATFORM_INFO);
658 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
659 power_limit_1_time = 28;
661 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
665 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
666 power_unit = 2 << ((msr.lo & 0xf) - 1);
668 /* Get power defaults for this SKU */
669 msr = msr_read(MSR_PKG_POWER_SKU);
670 tdp = msr.lo & 0x7fff;
671 min_power = (msr.lo >> 16) & 0x7fff;
672 max_power = msr.hi & 0x7fff;
673 max_time = (msr.hi >> 16) & 0x7f;
675 debug("CPU TDP: %u Watts\n", tdp / power_unit);
677 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
678 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
680 if (min_power > 0 && tdp < min_power)
683 if (max_power > 0 && tdp > max_power)
686 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
688 /* Set long term power limit to TDP */
690 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
691 limit.lo |= PKG_POWER_LIMIT_EN;
692 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
693 PKG_POWER_LIMIT_TIME_SHIFT;
695 /* Set short term power limit to 1.25 * TDP */
697 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
698 limit.hi |= PKG_POWER_LIMIT_EN;
699 /* Power limit 2 time is only programmable on server SKU */
701 msr_write(MSR_PKG_POWER_LIMIT, limit);
703 /* Set power limit values in MCHBAR as well */
704 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
705 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
707 /* Set DDR RAPL power limit by copying from MMIO to MSR */
708 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
709 msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
710 msr_write(MSR_DDR_RAPL_LIMIT, msr);
712 /* Use nominal TDP values for CPUs with configurable TDP */
713 if (cpu_config_tdp_levels()) {
714 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
716 limit.lo = msr.lo & 0xff;
717 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
721 static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
725 msr = msr_read(IA32_PERF_CTL);
726 info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
727 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
728 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
733 static int broadwell_get_count(struct udevice *dev)
738 static int cpu_x86_broadwell_probe(struct udevice *dev)
742 return broadwell_init(dev);
748 static const struct cpu_ops cpu_x86_broadwell_ops = {
749 .get_desc = cpu_x86_get_desc,
750 .get_info = broadwell_get_info,
751 .get_count = broadwell_get_count,
752 .get_vendor = cpu_x86_get_vendor,
755 static const struct udevice_id cpu_x86_broadwell_ids[] = {
756 { .compatible = "intel,core-i3-gen5" },
760 U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
761 .name = "cpu_x86_broadwell",
763 .of_match = cpu_x86_broadwell_ids,
764 .bind = cpu_x86_bind,
765 .probe = cpu_x86_broadwell_probe,
766 .ops = &cpu_x86_broadwell_ops,
767 .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),