1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
11 #include <asm/mrccache.h>
13 #include <asm/arch/iomap.h>
16 #define GPIO_SUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
17 #define GPIO_SUS_DFX5_CONF0 0x150
18 #define BYT_TRIG_LVL BIT(24)
19 #define BYT_TRIG_POS BIT(25)
21 int arch_cpu_init(void)
23 post_code(POST_CPU_INIT);
25 return x86_cpu_init_f();
28 int arch_misc_init(void)
33 #ifdef CONFIG_ENABLE_MRC_CACHE
35 * We intend not to check any return value here, as even MRC cache
36 * is not saved successfully, it is not a severe error that will
37 * prevent system from continuing to boot.
43 * For some unknown reason, FSP (gold4) for BayTrail configures
44 * the GPIO DFX5 PAD to enable level interrupt (bit 24 and 25).
45 * This does not cause any issue when Linux kernel runs w/ or w/o
46 * the pinctrl driver for BayTrail. However this causes unstable
47 * S3 resume if the pinctrl driver is included in the kernel build.
48 * As this pin keeps generating interrupts during an S3 resume,
49 * and there is no IRQ requester in the kernel to handle it, the
50 * kernel seems to hang and does not continue resuming.
52 * Clear the mysterious interrupt bits for this pin.
54 clrbits_le32(GPIO_SUS_PAD_BASE + GPIO_SUS_DFX5_CONF0,
55 BYT_TRIG_LVL | BYT_TRIG_POS);