2 * Copyright (C) 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
11 #define PCI_DEV_CONFIG(segbus, dev, fn) ( \
12 (((segbus) & 0xfff) << 20) | \
13 (((dev) & 0x1f) << 15) | \
14 (((fn) & 0x07) << 12))
16 /* Platform Controller Unit */
21 #define UART_CONT 0x80
23 /* SCORE Pad definitions */
24 #define UART_RXD_PAD 82
25 #define UART_TXD_PAD 83
27 /* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
28 #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
31 #define IO_BASE_ADDRESS 0xfed0c000
32 #define IO_BASE_OFFSET_GPSCORE 0x0000
33 #define IO_BASE_OFFSET_GPNCORE 0x1000
34 #define IO_BASE_OFFSET_GPSSUS 0x2000
35 #define IO_BASE_SIZE 0x4000
37 static inline unsigned int score_pconf0(int pad_num)
39 return GPSCORE_PAD_BASE + pad_num * 16;
42 static void score_select_func(int pad, int func)
45 uint32_t pconf0_addr = score_pconf0(pad);
47 reg = readl(pconf0_addr);
50 writel(reg, pconf0_addr);
53 static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
57 addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
61 /* This can be called after memory-mapped PCI is working */
62 int setup_early_uart(void)
64 /* Enable the legacy UART hardware. */
65 x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
69 * Set up the pads to the UART function. This allows the signals to
72 score_select_func(UART_RXD_PAD, 1);
73 score_select_func(UART_TXD_PAD, 1);
75 /* TODO(sjg@chromium.org): Call debug_uart_init() */