1 // SPDX-License-Identifier: GPL-2.0
3 * Special driver to handle of-platdata
5 * Copyright 2019 Google LLC
7 * Some code from coreboot lpss.c
12 #include <dt-structs.h>
19 /* Low-power Subsystem (LPSS) clock register */
21 LPSS_CLOCK_CTL_REG = 0x200,
22 LPSS_CNT_CLOCK_EN = 1,
23 LPSS_CNT_CLK_UPDATE = 1U << 31,
24 LPSS_CLOCK_DIV_N_SHIFT = 16,
25 LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT,
26 LPSS_CLOCK_DIV_M_SHIFT = 1,
27 LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT,
29 /* These set the UART input clock speed */
30 LPSS_UART_CLK_M_VAL = 0x25a,
31 LPSS_UART_CLK_N_VAL = 0x7fff,
34 static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val)
38 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT |
39 clk_m_val << LPSS_CLOCK_DIV_M_SHIFT;
40 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
42 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG);
45 static void uart_lpss_init(void *regs)
47 /* Take UART out of reset */
48 lpss_reset_release(regs);
50 /* Set M and N divisor inputs and enable clock */
51 lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL);
54 void apl_uart_init(pci_dev_t bdf, ulong base)
56 /* Set UART base address */
57 pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32);
59 /* Enable memory access and bus master */
60 pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY |
61 PCI_COMMAND_MASTER, PCI_SIZE_32);
63 uart_lpss_init((void *)base);
67 * This driver uses its own compatible string but almost everything else from
68 * the standard ns16550 driver. This allows us to provide an of-platdata
69 * implementation, since the platdata produced by of-platdata does not match
70 * struct ns16550_platdata.
72 * When running with of-platdata (generally TPL), the platdata is converted to
73 * something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
74 * proper), we use ns16550's ofdata_to_platdata routine.
77 static int apl_ns16550_probe(struct udevice *dev)
79 struct ns16550_platdata *plat = dev_get_platdata(dev);
81 if (!CONFIG_IS_ENABLED(PCI))
82 apl_uart_init(plat->bdf, plat->base);
84 return ns16550_serial_probe(dev);
87 static int apl_ns16550_ofdata_to_platdata(struct udevice *dev)
89 #if CONFIG_IS_ENABLED(OF_PLATDATA)
90 struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev);
91 struct ns16550_platdata *plat;
94 * Convert our platdata to the ns16550's platdata, so we can just use
97 plat = malloc(sizeof(*plat));
100 plat->base = dtplat->early_regs[0];
102 plat->reg_shift = dtplat->reg_shift;
103 plat->reg_offset = 0;
104 plat->clock = dtplat->clock_frequency;
105 plat->fcr = UART_FCR_DEFVAL;
106 plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
107 dev->platdata = plat;
111 ret = ns16550_serial_ofdata_to_platdata(dev);
114 #endif /* OF_PLATDATA */
119 static const struct udevice_id apl_ns16550_serial_ids[] = {
120 { .compatible = "intel,apl-ns16550" },
124 U_BOOT_DRIVER(apl_ns16550) = {
125 .name = "intel_apl_ns16550",
127 .of_match = apl_ns16550_serial_ids,
128 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
129 .priv_auto_alloc_size = sizeof(struct NS16550),
130 .ops = &ns16550_serial_ops,
131 .ofdata_to_platdata = apl_ns16550_ofdata_to_platdata,
132 .probe = apl_ns16550_probe,