1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google, LLC
4 * Written by Simon Glass <sjg@chromium.org>
13 * struct acpi_gpe_priv - private driver information
15 * @acpi_base: Base I/O address of ACPI registers
17 struct acpi_gpe_priv {
21 #define GPE0_STS(x) (0x20 + ((x) * 4))
23 static int acpi_gpe_read_and_clear(struct irq *irq)
25 struct acpi_gpe_priv *priv = dev_get_priv(irq->dev);
32 mask = 1 << (irq->id % 32);
34 /* Wait up to 1ms for GPE status to clear */
37 if (get_timer(start) > 1)
40 sts = inl(priv->acpi_base + GPE0_STS(bank));
42 outl(mask, priv->acpi_base + GPE0_STS(bank));
50 static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
52 struct acpi_gpe_priv *priv = dev_get_priv(dev);
54 priv->acpi_base = dev_read_addr(dev);
55 if (!priv->acpi_base || priv->acpi_base == FDT_ADDR_T_NONE)
56 return log_msg_ret("acpi_base", -EINVAL);
61 static int acpi_gpe_of_xlate(struct irq *irq, struct ofnode_phandle_args *args)
63 irq->id = args->args[0];
68 static const struct irq_ops acpi_gpe_ops = {
69 .read_and_clear = acpi_gpe_read_and_clear,
70 .of_xlate = acpi_gpe_of_xlate,
73 static const struct udevice_id acpi_gpe_ids[] = {
74 { .compatible = "intel,acpi-gpe", .data = X86_IRQT_ACPI_GPE },
78 U_BOOT_DRIVER(acpi_gpe_drv) = {
81 .of_match = acpi_gpe_ids,
83 .ofdata_to_platdata = acpi_gpe_ofdata_to_platdata,
84 .priv_auto_alloc_size = sizeof(struct acpi_gpe_priv),