1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
37 select SPL_SEPARATE_BSS
39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
40 experimental and many features are missing. U-Boot SPL starts up,
41 runs through the 16-bit and 32-bit init, then switches to 64-bit
42 mode and jumps to U-Boot proper.
54 prompt "Mainboard vendor"
55 default VENDOR_EMULATION
57 config VENDOR_ADVANTECH
60 config VENDOR_CONGATEC
63 config VENDOR_COREBOOT
72 config VENDOR_EMULATION
83 # board-specific options below
84 source "board/advantech/Kconfig"
85 source "board/congatec/Kconfig"
86 source "board/coreboot/Kconfig"
87 source "board/dfi/Kconfig"
88 source "board/efi/Kconfig"
89 source "board/emulation/Kconfig"
90 source "board/google/Kconfig"
91 source "board/intel/Kconfig"
93 # platform-specific options below
94 source "arch/x86/cpu/baytrail/Kconfig"
95 source "arch/x86/cpu/broadwell/Kconfig"
96 source "arch/x86/cpu/coreboot/Kconfig"
97 source "arch/x86/cpu/ivybridge/Kconfig"
98 source "arch/x86/cpu/qemu/Kconfig"
99 source "arch/x86/cpu/quark/Kconfig"
100 source "arch/x86/cpu/queensbay/Kconfig"
102 # architecture-specific options below
107 config SYS_MALLOC_F_LEN
116 depends on X86_RESET_VECTOR
125 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
134 config X86_RESET_VECTOR
138 # The following options control where the 16-bit and 32-bit init lies
139 # If SPL is enabled then it normally holds this init code, and U-Boot proper
140 # is normally a 64-bit build.
142 # The 16-bit init refers to the reset vector and the small amount of code to
143 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
144 # or missing altogether if U-Boot is started from EFI or coreboot.
146 # The 32-bit init refers to processor init, running binary blobs including
147 # FSP, setting up interrupts and anything else that needs to be done in
148 # 32-bit code. It is normally in the same place as 16-bit init if that is
149 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
150 config X86_16BIT_INIT
152 depends on X86_RESET_VECTOR
153 default y if X86_RESET_VECTOR && !SPL
155 This is enabled when 16-bit init is in U-Boot proper
157 config SPL_X86_16BIT_INIT
159 depends on X86_RESET_VECTOR
160 default y if X86_RESET_VECTOR && SPL
162 This is enabled when 16-bit init is in SPL
164 config X86_32BIT_INIT
166 depends on X86_RESET_VECTOR
167 default y if X86_RESET_VECTOR && !SPL
169 This is enabled when 32-bit init is in U-Boot proper
171 config SPL_X86_32BIT_INIT
173 depends on X86_RESET_VECTOR
174 default y if X86_RESET_VECTOR && SPL
176 This is enabled when 32-bit init is in SPL
178 config RESET_SEG_START
180 depends on X86_RESET_VECTOR
183 config RESET_SEG_SIZE
185 depends on X86_RESET_VECTOR
190 depends on X86_RESET_VECTOR
193 config SYS_X86_START16
195 depends on X86_RESET_VECTOR
198 config X86_LOAD_FROM_32_BIT
199 bool "Boot from a 32-bit program"
201 Define this to boot U-Boot from a 32-bit program which sets
202 the GDT differently. This can be used to boot directly from
203 any stage of coreboot, for example, bypassing the normal
204 payload-loading feature.
206 config BOARD_ROMSIZE_KB_512
208 config BOARD_ROMSIZE_KB_1024
210 config BOARD_ROMSIZE_KB_2048
212 config BOARD_ROMSIZE_KB_4096
214 config BOARD_ROMSIZE_KB_8192
216 config BOARD_ROMSIZE_KB_16384
220 prompt "ROM chip size"
221 depends on X86_RESET_VECTOR
222 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
223 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
224 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
225 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
226 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
227 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
229 Select the size of the ROM chip you intend to flash U-Boot on.
231 The build system will take care of creating a u-boot.rom file
232 of the matching size.
234 config UBOOT_ROMSIZE_KB_512
237 Choose this option if you have a 512 KB ROM chip.
239 config UBOOT_ROMSIZE_KB_1024
240 bool "1024 KB (1 MB)"
242 Choose this option if you have a 1024 KB (1 MB) ROM chip.
244 config UBOOT_ROMSIZE_KB_2048
245 bool "2048 KB (2 MB)"
247 Choose this option if you have a 2048 KB (2 MB) ROM chip.
249 config UBOOT_ROMSIZE_KB_4096
250 bool "4096 KB (4 MB)"
252 Choose this option if you have a 4096 KB (4 MB) ROM chip.
254 config UBOOT_ROMSIZE_KB_8192
255 bool "8192 KB (8 MB)"
257 Choose this option if you have a 8192 KB (8 MB) ROM chip.
259 config UBOOT_ROMSIZE_KB_16384
260 bool "16384 KB (16 MB)"
262 Choose this option if you have a 16384 KB (16 MB) ROM chip.
266 # Map the config names to an integer (KB).
267 config UBOOT_ROMSIZE_KB
269 default 512 if UBOOT_ROMSIZE_KB_512
270 default 1024 if UBOOT_ROMSIZE_KB_1024
271 default 2048 if UBOOT_ROMSIZE_KB_2048
272 default 4096 if UBOOT_ROMSIZE_KB_4096
273 default 8192 if UBOOT_ROMSIZE_KB_8192
274 default 16384 if UBOOT_ROMSIZE_KB_16384
276 # Map the config names to a hex value (bytes).
279 default 0x80000 if UBOOT_ROMSIZE_KB_512
280 default 0x100000 if UBOOT_ROMSIZE_KB_1024
281 default 0x200000 if UBOOT_ROMSIZE_KB_2048
282 default 0x400000 if UBOOT_ROMSIZE_KB_4096
283 default 0x800000 if UBOOT_ROMSIZE_KB_8192
284 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
285 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
288 bool "Platform requires Intel Management Engine"
290 Newer higher-end devices have an Intel Management Engine (ME)
291 which is a very large binary blob (typically 1.5MB) which is
292 required for the platform to work. This enforces a particular
293 SPI flash format. You will need to supply the me.bin file in
294 your board directory.
297 bool "Perform a simple RAM test after SDRAM initialisation"
299 If there is something wrong with SDRAM then the platform will
300 often crash within U-Boot or the kernel. This option enables a
301 very simple RAM test that quickly checks whether the SDRAM seems
302 to work correctly. It is not exhaustive but can save time by
303 detecting obvious failures.
306 bool "Add an Firmware Support Package binary"
309 Select this option to add an Firmware Support Package binary to
310 the resulting U-Boot image. It is a binary blob which U-Boot uses
311 to set up SDRAM and other chipset specific initialization.
313 Note: Without this binary U-Boot will not be able to set up its
314 SDRAM so will not boot.
317 string "Firmware Support Package binary filename"
321 The filename of the file to use as Firmware Support Package binary
322 in the board directory.
325 hex "Firmware Support Package binary location"
329 FSP is not Position Independent Code (PIC) and the whole FSP has to
330 be rebased if it is placed at a location which is different from the
331 perferred base address specified during the FSP build. Use Intel's
332 Binary Configuration Tool (BCT) to do the rebase.
334 The default base address of 0xfffc0000 indicates that the binary must
335 be located at offset 0xc0000 from the beginning of a 1MB flash device.
337 config FSP_TEMP_RAM_ADDR
342 Stack top address which is used in fsp_init() after DRAM is ready and
345 config FSP_SYS_MALLOC_F_LEN
350 Additional size of malloc() pool before relocation.
357 Most FSPs use UPD data region for some FSP customization. But there
358 are still some FSPs that might not even have UPD. For such FSPs,
359 override this to n in their platform Kconfig files.
361 config FSP_BROKEN_HOB
365 Indicate some buggy FSPs that does not report memory used by FSP
366 itself as reserved in the resource descriptor HOB. Select this to
367 tell U-Boot to do some additional work to ensure U-Boot relocation
368 do not overwrite the important boot service data which is used by
369 FSP, otherwise the subsequent call to fsp_notify() will fail.
371 config ENABLE_MRC_CACHE
372 bool "Enable MRC cache"
373 depends on !EFI && !SYS_COREBOOT
375 Enable this feature to cause MRC data to be cached in NV storage
376 to be used for speeding up boot time on future reboots and/or
379 For platforms that use Intel FSP for the memory initialization,
380 please check FSP output HOB via U-Boot command 'fsp hob' to see
381 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
382 If such GUID does not exist, MRC cache is not avaiable on such
383 platform (eg: Intel Queensbay), which means selecting this option
384 here does not make any difference.
387 bool "Add a System Agent binary"
390 Select this option to add a System Agent binary to
391 the resulting U-Boot image. MRC stands for Memory Reference Code.
392 It is a binary blob which U-Boot uses to set up SDRAM.
394 Note: Without this binary U-Boot will not be able to set up its
395 SDRAM so will not boot.
402 Enable caching for the memory reference code binary. This uses an
403 MTRR (memory type range register) to turn on caching for the section
404 of SPI flash that contains the memory reference code. This makes
405 SDRAM init run faster.
407 config CACHE_MRC_SIZE_KB
412 Sets the size of the cached area for the memory reference code.
413 This ends at the end of SPI flash (address 0xffffffff) and is
414 measured in KB. Typically this is set to 512, providing for 0.5MB
417 config DCACHE_RAM_BASE
421 Sets the base of the data cache area in memory space. This is the
422 start address of the cache-as-RAM (CAR) area and the address varies
423 depending on the CPU. Once CAR is set up, read/write memory becomes
424 available at this address and can be used temporarily until SDRAM
427 config DCACHE_RAM_SIZE
432 Sets the total size of the data cache area in memory space. This
433 sets the size of the cache-as-RAM (CAR) area. Note that much of the
434 CAR space is required by the MRC. The CAR space available to U-Boot
435 is normally at the start and typically extends to 1/4 or 1/2 of the
438 config DCACHE_RAM_MRC_VAR_SIZE
442 This is the amount of CAR (Cache as RAM) reserved for use by the
443 memory reference code. This depends on the implementation of the
444 memory reference code and must be set correctly or the board will
448 bool "Add a Reference Code binary"
450 Select this option to add a Reference Code binary to the resulting
451 U-Boot image. This is an Intel binary blob that handles system
452 initialisation, in this case the PCH and System Agent.
454 Note: Without this binary (on platforms that need it such as
455 broadwell) U-Boot will be missing some critical setup steps.
456 Various peripherals may fail to work.
459 bool "Enable Symmetric Multiprocessing"
462 Enable use of more than one CPU in U-Boot and the Operating System
463 when loaded. Each CPU will be started up and information can be
464 obtained using the 'cpu' command. If this option is disabled, then
465 only one CPU will be enabled regardless of the number of CPUs
469 int "Maximum number of CPUs permitted"
473 When using multi-CPU chips it is possible for U-Boot to start up
474 more than one CPU. The stack memory used by all of these CPUs is
475 pre-allocated so at present U-Boot wants to know the maximum
476 number of CPUs that may be present. Set this to at least as high
477 as the number of CPUs in your system (it uses about 4KB of RAM for
485 Each additional CPU started by U-Boot requires its own stack. This
486 option sets the stack size used by each CPU and directly affects
487 the memory used by this initialisation process. Typically 4KB is
491 bool "Add a VGA BIOS image"
493 Select this option if you have a VGA BIOS image that you would
494 like to add to your ROM.
497 string "VGA BIOS image filename"
498 depends on HAVE_VGA_BIOS
501 The filename of the VGA BIOS image in the board directory.
504 hex "VGA BIOS image location"
505 depends on HAVE_VGA_BIOS
508 The location of VGA BIOS image in the SPI flash. For example, base
509 address of 0xfff90000 indicates that the image will be put at offset
510 0x90000 from the beginning of a 1MB flash device.
513 depends on !EFI && !SYS_COREBOOT
515 config GENERATE_PIRQ_TABLE
516 bool "Generate a PIRQ table"
519 Generate a PIRQ routing table for this board. The PIRQ routing table
520 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
521 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
522 It specifies the interrupt router information as well how all the PCI
523 devices' interrupt pins are wired to PIRQs.
525 config GENERATE_SFI_TABLE
526 bool "Generate a SFI (Simple Firmware Interface) table"
528 The Simple Firmware Interface (SFI) provides a lightweight method
529 for platform firmware to pass information to the operating system
530 via static tables in memory. Kernel SFI support is required to
531 boot on SFI-only platforms. If you have ACPI tables then these are
534 U-Boot writes this table in write_sfi_table() just before booting
537 For more information, see http://simplefirmware.org
539 config GENERATE_MP_TABLE
540 bool "Generate an MP (Multi-Processor) table"
543 Generate an MP (Multi-Processor) table for this board. The MP table
544 provides a way for the operating system to support for symmetric
545 multiprocessing as well as symmetric I/O interrupt handling with
546 the local APIC and I/O APIC.
548 config GENERATE_ACPI_TABLE
549 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
553 The Advanced Configuration and Power Interface (ACPI) specification
554 provides an open standard for device configuration and management
555 by the operating system. It defines platform-independent interfaces
556 for configuration and power management monitoring.
560 config MAX_PIRQ_LINKS
564 This variable specifies the number of PIRQ interrupt links which are
565 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
566 Some newer chipsets offer more than four links, commonly up to PIRQH.
568 config IRQ_SLOT_COUNT
572 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
573 which in turns forms a table of exact 4KiB. The default value 128
574 should be enough for most boards. If this does not fit your board,
575 change it according to your needs.
577 config PCIE_ECAM_BASE
581 This is the memory-mapped address of PCI configuration space, which
582 is only available through the Enhanced Configuration Access
583 Mechanism (ECAM) with PCI Express. It can be set up almost
584 anywhere. Before it is set up, it is possible to access PCI
585 configuration space through I/O access, but memory access is more
586 convenient. Using this, PCI can be scanned and configured. This
587 should be set to a region that does not conflict with memory
588 assigned to PCI devices - i.e. the memory and prefetch regions, as
589 passed to pci_set_region().
591 config PCIE_ECAM_SIZE
595 This is the size of memory-mapped address of PCI configuration space,
596 which is only available through the Enhanced Configuration Access
597 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
598 so a default 0x10000000 size covers all of the 256 buses which is the
599 maximum number of PCI buses as defined by the PCI specification.
605 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
606 slave) interrupt controllers. Include this to have U-Boot set up
607 the interrupt correctly.
613 Intel 8254 timer contains three counters which have fixed uses.
614 Include this to have U-Boot set up the timer correctly.
617 bool "Support booting SeaBIOS"
619 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
620 It can run in an emulator or natively on X86 hardware with the use
621 of coreboot/U-Boot. By turning on this option, U-Boot prepares
622 all the configuration tables that are necessary to boot SeaBIOS.
624 Check http://www.seabios.org/SeaBIOS for details.
626 config HIGH_TABLE_SIZE
627 hex "Size of configuration tables which reside in high memory"
631 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
632 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
633 puts a copy of configuration tables in high memory region which
634 is reserved on the stack before relocation. The region size is
635 determined by this option.
637 Increse it if the default size does not fit the board's needs.
638 This is most likely due to a large ACPI DSDT table is used.
640 source "arch/x86/lib/efi/Kconfig"