1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
36 select SPL_SEPARATE_BSS
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
56 config VENDOR_ADVANTECH
59 config VENDOR_CONGATEC
62 config VENDOR_COREBOOT
71 config VENDOR_EMULATION
82 # subarchitectures-specific options below
84 bool "Intel MID platform support"
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
92 If you are building for a PC class system say N here.
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
98 # board-specific options below
99 source "board/advantech/Kconfig"
100 source "board/congatec/Kconfig"
101 source "board/coreboot/Kconfig"
102 source "board/dfi/Kconfig"
103 source "board/efi/Kconfig"
104 source "board/emulation/Kconfig"
105 source "board/google/Kconfig"
106 source "board/intel/Kconfig"
108 # platform-specific options below
109 source "arch/x86/cpu/baytrail/Kconfig"
110 source "arch/x86/cpu/braswell/Kconfig"
111 source "arch/x86/cpu/broadwell/Kconfig"
112 source "arch/x86/cpu/coreboot/Kconfig"
113 source "arch/x86/cpu/ivybridge/Kconfig"
114 source "arch/x86/cpu/efi/Kconfig"
115 source "arch/x86/cpu/qemu/Kconfig"
116 source "arch/x86/cpu/quark/Kconfig"
117 source "arch/x86/cpu/queensbay/Kconfig"
118 source "arch/x86/cpu/slimbootloader/Kconfig"
119 source "arch/x86/cpu/tangier/Kconfig"
121 # architecture-specific options below
126 config SYS_MALLOC_F_LEN
135 depends on X86_RESET_VECTOR
144 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
153 config X86_RESET_VECTOR
158 # The following options control where the 16-bit and 32-bit init lies
159 # If SPL is enabled then it normally holds this init code, and U-Boot proper
160 # is normally a 64-bit build.
162 # The 16-bit init refers to the reset vector and the small amount of code to
163 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
164 # or missing altogether if U-Boot is started from EFI or coreboot.
166 # The 32-bit init refers to processor init, running binary blobs including
167 # FSP, setting up interrupts and anything else that needs to be done in
168 # 32-bit code. It is normally in the same place as 16-bit init if that is
169 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
170 config X86_16BIT_INIT
172 depends on X86_RESET_VECTOR
173 default y if X86_RESET_VECTOR && !SPL
175 This is enabled when 16-bit init is in U-Boot proper
177 config SPL_X86_16BIT_INIT
179 depends on X86_RESET_VECTOR
180 default y if X86_RESET_VECTOR && SPL && !TPL
182 This is enabled when 16-bit init is in SPL
184 config TPL_X86_16BIT_INIT
186 depends on X86_RESET_VECTOR
187 default y if X86_RESET_VECTOR && TPL
189 This is enabled when 16-bit init is in TPL
191 config X86_32BIT_INIT
193 depends on X86_RESET_VECTOR
194 default y if X86_RESET_VECTOR && !SPL
196 This is enabled when 32-bit init is in U-Boot proper
198 config SPL_X86_32BIT_INIT
200 depends on X86_RESET_VECTOR
201 default y if X86_RESET_VECTOR && SPL
203 This is enabled when 32-bit init is in SPL
205 config RESET_SEG_START
207 depends on X86_RESET_VECTOR
210 config RESET_SEG_SIZE
212 depends on X86_RESET_VECTOR
217 depends on X86_RESET_VECTOR
220 config SYS_X86_START16
222 depends on X86_RESET_VECTOR
225 config X86_LOAD_FROM_32_BIT
226 bool "Boot from a 32-bit program"
228 Define this to boot U-Boot from a 32-bit program which sets
229 the GDT differently. This can be used to boot directly from
230 any stage of coreboot, for example, bypassing the normal
231 payload-loading feature.
233 config BOARD_ROMSIZE_KB_512
235 config BOARD_ROMSIZE_KB_1024
237 config BOARD_ROMSIZE_KB_2048
239 config BOARD_ROMSIZE_KB_4096
241 config BOARD_ROMSIZE_KB_8192
243 config BOARD_ROMSIZE_KB_16384
247 prompt "ROM chip size"
248 depends on X86_RESET_VECTOR
249 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
250 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
251 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
252 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
253 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
254 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
256 Select the size of the ROM chip you intend to flash U-Boot on.
258 The build system will take care of creating a u-boot.rom file
259 of the matching size.
261 config UBOOT_ROMSIZE_KB_512
264 Choose this option if you have a 512 KB ROM chip.
266 config UBOOT_ROMSIZE_KB_1024
267 bool "1024 KB (1 MB)"
269 Choose this option if you have a 1024 KB (1 MB) ROM chip.
271 config UBOOT_ROMSIZE_KB_2048
272 bool "2048 KB (2 MB)"
274 Choose this option if you have a 2048 KB (2 MB) ROM chip.
276 config UBOOT_ROMSIZE_KB_4096
277 bool "4096 KB (4 MB)"
279 Choose this option if you have a 4096 KB (4 MB) ROM chip.
281 config UBOOT_ROMSIZE_KB_8192
282 bool "8192 KB (8 MB)"
284 Choose this option if you have a 8192 KB (8 MB) ROM chip.
286 config UBOOT_ROMSIZE_KB_16384
287 bool "16384 KB (16 MB)"
289 Choose this option if you have a 16384 KB (16 MB) ROM chip.
293 # Map the config names to an integer (KB).
294 config UBOOT_ROMSIZE_KB
296 default 512 if UBOOT_ROMSIZE_KB_512
297 default 1024 if UBOOT_ROMSIZE_KB_1024
298 default 2048 if UBOOT_ROMSIZE_KB_2048
299 default 4096 if UBOOT_ROMSIZE_KB_4096
300 default 8192 if UBOOT_ROMSIZE_KB_8192
301 default 16384 if UBOOT_ROMSIZE_KB_16384
303 # Map the config names to a hex value (bytes).
306 default 0x80000 if UBOOT_ROMSIZE_KB_512
307 default 0x100000 if UBOOT_ROMSIZE_KB_1024
308 default 0x200000 if UBOOT_ROMSIZE_KB_2048
309 default 0x400000 if UBOOT_ROMSIZE_KB_4096
310 default 0x800000 if UBOOT_ROMSIZE_KB_8192
311 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
312 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
315 bool "Platform requires Intel Management Engine"
317 Newer higher-end devices have an Intel Management Engine (ME)
318 which is a very large binary blob (typically 1.5MB) which is
319 required for the platform to work. This enforces a particular
320 SPI flash format. You will need to supply the me.bin file in
321 your board directory.
324 bool "Perform a simple RAM test after SDRAM initialisation"
326 If there is something wrong with SDRAM then the platform will
327 often crash within U-Boot or the kernel. This option enables a
328 very simple RAM test that quickly checks whether the SDRAM seems
329 to work correctly. It is not exhaustive but can save time by
330 detecting obvious failures.
332 config FLASH_DESCRIPTOR_FILE
333 string "Flash descriptor binary filename"
334 depends on HAVE_INTEL_ME
335 default "descriptor.bin"
337 The filename of the file to use as flash descriptor in the
341 string "Intel Management Engine binary filename"
342 depends on HAVE_INTEL_ME
345 The filename of the file to use as Intel Management Engine in the
349 bool "Use HOB (Hand-Off Block)"
351 Select this option to access HOB (Hand-Off Block) data structures
352 and parse HOBs. This HOB infra structure can be reused with
353 different solutions across different platforms.
356 bool "Add an Firmware Support Package binary"
360 Select this option to add an Firmware Support Package binary to
361 the resulting U-Boot image. It is a binary blob which U-Boot uses
362 to set up SDRAM and other chipset specific initialization.
364 Note: Without this binary U-Boot will not be able to set up its
365 SDRAM so will not boot.
368 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
369 default y if !HAVE_FSP
371 Select this option if your board uses CAR init code, typically in a
372 car.S file, to get some initial memory for code execution. This is
373 common with Intel CPUs which don't use FSP.
380 Selects the FSP version to use. Intel has published several versions
381 of the FSP External Architecture Specification and this allows
382 selection of the version number used by a particular SoC.
385 bool "FSP version 1.x"
387 This covers versions 1.0 and 1.1a. See here for details:
388 https://github.com/IntelFsp/fsp/wiki
391 bool "FSP version 2.x"
393 This covers versions 2.0 and 2.1. See here for details:
394 https://github.com/IntelFsp/fsp/wiki
399 string "Firmware Support Package binary filename"
403 The filename of the file to use as Firmware Support Package binary
404 in the board directory.
407 hex "Firmware Support Package binary location"
411 FSP is not Position Independent Code (PIC) and the whole FSP has to
412 be rebased if it is placed at a location which is different from the
413 perferred base address specified during the FSP build. Use Intel's
414 Binary Configuration Tool (BCT) to do the rebase.
416 The default base address of 0xfffc0000 indicates that the binary must
417 be located at offset 0xc0000 from the beginning of a 1MB flash device.
419 config FSP_TEMP_RAM_ADDR
424 Stack top address which is used in fsp_init() after DRAM is ready and
427 config FSP_SYS_MALLOC_F_LEN
432 Additional size of malloc() pool before relocation.
439 Most FSPs use UPD data region for some FSP customization. But there
440 are still some FSPs that might not even have UPD. For such FSPs,
441 override this to n in their platform Kconfig files.
443 config FSP_BROKEN_HOB
447 Indicate some buggy FSPs that does not report memory used by FSP
448 itself as reserved in the resource descriptor HOB. Select this to
449 tell U-Boot to do some additional work to ensure U-Boot relocation
450 do not overwrite the important boot service data which is used by
451 FSP, otherwise the subsequent call to fsp_notify() will fail.
453 config ENABLE_MRC_CACHE
454 bool "Enable MRC cache"
455 depends on !EFI && !SYS_COREBOOT
457 Enable this feature to cause MRC data to be cached in NV storage
458 to be used for speeding up boot time on future reboots and/or
461 For platforms that use Intel FSP for the memory initialization,
462 please check FSP output HOB via U-Boot command 'fsp hob' to see
463 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
464 If such GUID does not exist, MRC cache is not available on such
465 platform (eg: Intel Queensbay), which means selecting this option
466 here does not make any difference.
469 bool "Add a System Agent binary"
472 Select this option to add a System Agent binary to
473 the resulting U-Boot image. MRC stands for Memory Reference Code.
474 It is a binary blob which U-Boot uses to set up SDRAM.
476 Note: Without this binary U-Boot will not be able to set up its
477 SDRAM so will not boot.
484 Enable caching for the memory reference code binary. This uses an
485 MTRR (memory type range register) to turn on caching for the section
486 of SPI flash that contains the memory reference code. This makes
487 SDRAM init run faster.
489 config CACHE_MRC_SIZE_KB
494 Sets the size of the cached area for the memory reference code.
495 This ends at the end of SPI flash (address 0xffffffff) and is
496 measured in KB. Typically this is set to 512, providing for 0.5MB
499 config DCACHE_RAM_BASE
503 Sets the base of the data cache area in memory space. This is the
504 start address of the cache-as-RAM (CAR) area and the address varies
505 depending on the CPU. Once CAR is set up, read/write memory becomes
506 available at this address and can be used temporarily until SDRAM
509 config DCACHE_RAM_SIZE
514 Sets the total size of the data cache area in memory space. This
515 sets the size of the cache-as-RAM (CAR) area. Note that much of the
516 CAR space is required by the MRC. The CAR space available to U-Boot
517 is normally at the start and typically extends to 1/4 or 1/2 of the
520 config DCACHE_RAM_MRC_VAR_SIZE
524 This is the amount of CAR (Cache as RAM) reserved for use by the
525 memory reference code. This depends on the implementation of the
526 memory reference code and must be set correctly or the board will
530 bool "Add a Reference Code binary"
532 Select this option to add a Reference Code binary to the resulting
533 U-Boot image. This is an Intel binary blob that handles system
534 initialisation, in this case the PCH and System Agent.
536 Note: Without this binary (on platforms that need it such as
537 broadwell) U-Boot will be missing some critical setup steps.
538 Various peripherals may fail to work.
541 bool "Enable Symmetric Multiprocessing"
544 Enable use of more than one CPU in U-Boot and the Operating System
545 when loaded. Each CPU will be started up and information can be
546 obtained using the 'cpu' command. If this option is disabled, then
547 only one CPU will be enabled regardless of the number of CPUs
551 int "Maximum number of CPUs permitted"
555 When using multi-CPU chips it is possible for U-Boot to start up
556 more than one CPU. The stack memory used by all of these CPUs is
557 pre-allocated so at present U-Boot wants to know the maximum
558 number of CPUs that may be present. Set this to at least as high
559 as the number of CPUs in your system (it uses about 4KB of RAM for
567 Each additional CPU started by U-Boot requires its own stack. This
568 option sets the stack size used by each CPU and directly affects
569 the memory used by this initialisation process. Typically 4KB is
572 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
575 This option indicates that the turbo mode setting is not package
576 scoped. i.e. turbo_enable() needs to be called on not just the
577 bootstrap processor (BSP).
580 bool "Add a VGA BIOS image"
582 Select this option if you have a VGA BIOS image that you would
583 like to add to your ROM.
586 string "VGA BIOS image filename"
587 depends on HAVE_VGA_BIOS
590 The filename of the VGA BIOS image in the board directory.
593 hex "VGA BIOS image location"
594 depends on HAVE_VGA_BIOS
597 The location of VGA BIOS image in the SPI flash. For example, base
598 address of 0xfff90000 indicates that the image will be put at offset
599 0x90000 from the beginning of a 1MB flash device.
602 bool "Add a Video BIOS Table (VBT) image"
605 Select this option if you have a Video BIOS Table (VBT) image that
606 you would like to add to your ROM. This is normally required if you
607 are using an Intel FSP firmware that is complaint with spec 1.1 or
608 later to initialize the integrated graphics device (IGD).
610 Video BIOS Table, or VBT, provides platform and board specific
611 configuration information to the driver that is not discoverable
612 or available through other means. By other means the most used
613 method here is to read EDID table from the attached monitor, over
614 Display Data Channel (DDC) using two pin I2C serial interface. VBT
615 configuration is related to display hardware and is available via
616 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
619 string "Video BIOS Table (VBT) image filename"
623 The filename of the file to use as Video BIOS Table (VBT) image
624 in the board directory.
627 hex "Video BIOS Table (VBT) image location"
631 The location of Video BIOS Table (VBT) image in the SPI flash. For
632 example, base address of 0xfff90000 indicates that the image will
633 be put at offset 0x90000 from the beginning of a 1MB flash device.
636 bool "Enable FSP framebuffer driver support"
637 depends on HAVE_VBT && DM_VIDEO
639 Turn on this option to enable a framebuffer driver when U-Boot is
640 using Video BIOS Table (VBT) image for FSP firmware to initialize
641 the integrated graphics device.
643 config ROM_TABLE_ADDR
647 All x86 tables happen to like the address range from 0x0f0000
648 to 0x100000. We use 0xf0000 as the starting address to store
649 those tables, including PIRQ routing table, Multi-Processor
650 table and ACPI table.
652 config ROM_TABLE_SIZE
657 depends on !EFI && !SYS_COREBOOT
659 config GENERATE_PIRQ_TABLE
660 bool "Generate a PIRQ table"
663 Generate a PIRQ routing table for this board. The PIRQ routing table
664 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
665 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
666 It specifies the interrupt router information as well how all the PCI
667 devices' interrupt pins are wired to PIRQs.
669 config GENERATE_SFI_TABLE
670 bool "Generate a SFI (Simple Firmware Interface) table"
672 The Simple Firmware Interface (SFI) provides a lightweight method
673 for platform firmware to pass information to the operating system
674 via static tables in memory. Kernel SFI support is required to
675 boot on SFI-only platforms. If you have ACPI tables then these are
678 U-Boot writes this table in write_sfi_table() just before booting
681 For more information, see http://simplefirmware.org
683 config GENERATE_MP_TABLE
684 bool "Generate an MP (Multi-Processor) table"
687 Generate an MP (Multi-Processor) table for this board. The MP table
688 provides a way for the operating system to support for symmetric
689 multiprocessing as well as symmetric I/O interrupt handling with
690 the local APIC and I/O APIC.
692 config GENERATE_ACPI_TABLE
693 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
697 The Advanced Configuration and Power Interface (ACPI) specification
698 provides an open standard for device configuration and management
699 by the operating system. It defines platform-independent interfaces
700 for configuration and power management monitoring.
704 config HAVE_ACPI_RESUME
705 bool "Enable ACPI S3 resume"
706 select ENABLE_MRC_CACHE
708 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
709 state where all system context is lost except system memory. U-Boot
710 is responsible for restoring the machine state as it was before sleep.
711 It needs restore the memory controller, without overwriting memory
712 which is not marked as reserved. For the peripherals which lose their
713 registers, U-Boot needs to write the original value. When everything
714 is done, U-Boot needs to find out the wakeup vector provided by OSes
717 config S3_VGA_ROM_RUN
718 bool "Re-run VGA option ROMs on S3 resume"
719 depends on HAVE_ACPI_RESUME
721 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
722 this is needed when graphics console is being used in the kernel.
724 Turning it off can reduce some resume time, but be aware that your
725 graphics console won't work without VGA options ROMs. Set it to N
726 if your kernel is only on a serial console.
730 depends on HAVE_ACPI_RESUME
733 Estimated U-Boot's runtime stack size that needs to be reserved
734 during an ACPI S3 resume.
736 config MAX_PIRQ_LINKS
740 This variable specifies the number of PIRQ interrupt links which are
741 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
742 Some newer chipsets offer more than four links, commonly up to PIRQH.
744 config IRQ_SLOT_COUNT
748 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
749 which in turns forms a table of exact 4KiB. The default value 128
750 should be enough for most boards. If this does not fit your board,
751 change it according to your needs.
753 config PCIE_ECAM_BASE
757 This is the memory-mapped address of PCI configuration space, which
758 is only available through the Enhanced Configuration Access
759 Mechanism (ECAM) with PCI Express. It can be set up almost
760 anywhere. Before it is set up, it is possible to access PCI
761 configuration space through I/O access, but memory access is more
762 convenient. Using this, PCI can be scanned and configured. This
763 should be set to a region that does not conflict with memory
764 assigned to PCI devices - i.e. the memory and prefetch regions, as
765 passed to pci_set_region().
767 config PCIE_ECAM_SIZE
771 This is the size of memory-mapped address of PCI configuration space,
772 which is only available through the Enhanced Configuration Access
773 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
774 so a default 0x10000000 size covers all of the 256 buses which is the
775 maximum number of PCI buses as defined by the PCI specification.
778 bool "Enable Intel 8259 compatible interrupt controller"
781 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
782 slave) interrupt controllers. Include this to have U-Boot set up
783 the interrupt correctly.
786 bool "Enable Intel Advanced Programmable Interrupt Controller"
789 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
790 for catching interrupts and distributing them to one or more CPU
791 cores. In most cases there are some LAPICs (local) for each core and
792 one I/O APIC. This conjunction is found on most modern x86 systems.
797 Intel ICH6 compatible chipset pinctrl driver. It needs to work
798 together with the ICH6 compatible gpio driver.
804 Intel 8254 timer contains three counters which have fixed uses.
805 Include this to have U-Boot set up the timer correctly.
808 bool "Support booting SeaBIOS"
810 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
811 It can run in an emulator or natively on X86 hardware with the use
812 of coreboot/U-Boot. By turning on this option, U-Boot prepares
813 all the configuration tables that are necessary to boot SeaBIOS.
815 Check http://www.seabios.org/SeaBIOS for details.
817 config HIGH_TABLE_SIZE
818 hex "Size of configuration tables which reside in high memory"
822 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
823 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
824 puts a copy of configuration tables in high memory region which
825 is reserved on the stack before relocation. The region size is
826 determined by this option.
828 Increse it if the default size does not fit the board's needs.
829 This is most likely due to a large ACPI DSDT table is used.