1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
14 prompt "Mainboard vendor"
15 default VENDOR_COREBOOT
17 config VENDOR_COREBOOT
28 # board-specific options below
29 source "board/coreboot/Kconfig"
30 source "board/google/Kconfig"
31 source "board/intel/Kconfig"
33 # platform-specific options below
34 source "arch/x86/cpu/baytrail/Kconfig"
35 source "arch/x86/cpu/coreboot/Kconfig"
36 source "arch/x86/cpu/ivybridge/Kconfig"
37 source "arch/x86/cpu/quark/Kconfig"
38 source "arch/x86/cpu/queensbay/Kconfig"
40 # architecture-specific options below
48 config SYS_MALLOC_F_LEN
57 depends on X86_RESET_VECTOR
66 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
75 config X86_RESET_VECTOR
79 config SYS_X86_START16
81 depends on X86_RESET_VECTOR
84 config BOARD_ROMSIZE_KB_512
86 config BOARD_ROMSIZE_KB_1024
88 config BOARD_ROMSIZE_KB_2048
90 config BOARD_ROMSIZE_KB_4096
92 config BOARD_ROMSIZE_KB_8192
94 config BOARD_ROMSIZE_KB_16384
98 prompt "ROM chip size"
99 depends on X86_RESET_VECTOR
100 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
101 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
102 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
103 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
104 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
105 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
107 Select the size of the ROM chip you intend to flash U-Boot on.
109 The build system will take care of creating a u-boot.rom file
110 of the matching size.
112 config UBOOT_ROMSIZE_KB_512
115 Choose this option if you have a 512 KB ROM chip.
117 config UBOOT_ROMSIZE_KB_1024
118 bool "1024 KB (1 MB)"
120 Choose this option if you have a 1024 KB (1 MB) ROM chip.
122 config UBOOT_ROMSIZE_KB_2048
123 bool "2048 KB (2 MB)"
125 Choose this option if you have a 2048 KB (2 MB) ROM chip.
127 config UBOOT_ROMSIZE_KB_4096
128 bool "4096 KB (4 MB)"
130 Choose this option if you have a 4096 KB (4 MB) ROM chip.
132 config UBOOT_ROMSIZE_KB_8192
133 bool "8192 KB (8 MB)"
135 Choose this option if you have a 8192 KB (8 MB) ROM chip.
137 config UBOOT_ROMSIZE_KB_16384
138 bool "16384 KB (16 MB)"
140 Choose this option if you have a 16384 KB (16 MB) ROM chip.
144 # Map the config names to an integer (KB).
145 config UBOOT_ROMSIZE_KB
147 default 512 if UBOOT_ROMSIZE_KB_512
148 default 1024 if UBOOT_ROMSIZE_KB_1024
149 default 2048 if UBOOT_ROMSIZE_KB_2048
150 default 4096 if UBOOT_ROMSIZE_KB_4096
151 default 8192 if UBOOT_ROMSIZE_KB_8192
152 default 16384 if UBOOT_ROMSIZE_KB_16384
154 # Map the config names to a hex value (bytes).
157 default 0x80000 if UBOOT_ROMSIZE_KB_512
158 default 0x100000 if UBOOT_ROMSIZE_KB_1024
159 default 0x200000 if UBOOT_ROMSIZE_KB_2048
160 default 0x400000 if UBOOT_ROMSIZE_KB_4096
161 default 0x800000 if UBOOT_ROMSIZE_KB_8192
162 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
163 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
166 bool "Platform requires Intel Management Engine"
168 Newer higher-end devices have an Intel Management Engine (ME)
169 which is a very large binary blob (typically 1.5MB) which is
170 required for the platform to work. This enforces a particular
171 SPI flash format. You will need to supply the me.bin file in
172 your board directory.
175 bool "Perform a simple RAM test after SDRAM initialisation"
177 If there is something wrong with SDRAM then the platform will
178 often crash within U-Boot or the kernel. This option enables a
179 very simple RAM test that quickly checks whether the SDRAM seems
180 to work correctly. It is not exhaustive but can save time by
181 detecting obvious failures.
183 config MARK_GRAPHICS_MEM_WRCOMB
184 bool "Mark graphics memory as write-combining."
187 The graphics performance may increase if the graphics
188 memory is set as write-combining cache type. This option
189 enables marking the graphics memory as write-combining.
193 config FRAMEBUFFER_SET_VESA_MODE
194 prompt "Set framebuffer graphics resolution"
197 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
200 prompt "framebuffer graphics resolution"
201 default FRAMEBUFFER_VESA_MODE_117
202 depends on FRAMEBUFFER_SET_VESA_MODE
204 This option sets the resolution used for the coreboot framebuffer (and
207 config FRAMEBUFFER_VESA_MODE_100
208 bool "640x400 256-color"
210 config FRAMEBUFFER_VESA_MODE_101
211 bool "640x480 256-color"
213 config FRAMEBUFFER_VESA_MODE_102
214 bool "800x600 16-color"
216 config FRAMEBUFFER_VESA_MODE_103
217 bool "800x600 256-color"
219 config FRAMEBUFFER_VESA_MODE_104
220 bool "1024x768 16-color"
222 config FRAMEBUFFER_VESA_MODE_105
223 bool "1024x7686 256-color"
225 config FRAMEBUFFER_VESA_MODE_106
226 bool "1280x1024 16-color"
228 config FRAMEBUFFER_VESA_MODE_107
229 bool "1280x1024 256-color"
231 config FRAMEBUFFER_VESA_MODE_108
234 config FRAMEBUFFER_VESA_MODE_109
237 config FRAMEBUFFER_VESA_MODE_10A
240 config FRAMEBUFFER_VESA_MODE_10B
243 config FRAMEBUFFER_VESA_MODE_10C
246 config FRAMEBUFFER_VESA_MODE_10D
247 bool "320x200 32k-color (1:5:5:5)"
249 config FRAMEBUFFER_VESA_MODE_10E
250 bool "320x200 64k-color (5:6:5)"
252 config FRAMEBUFFER_VESA_MODE_10F
253 bool "320x200 16.8M-color (8:8:8)"
255 config FRAMEBUFFER_VESA_MODE_110
256 bool "640x480 32k-color (1:5:5:5)"
258 config FRAMEBUFFER_VESA_MODE_111
259 bool "640x480 64k-color (5:6:5)"
261 config FRAMEBUFFER_VESA_MODE_112
262 bool "640x480 16.8M-color (8:8:8)"
264 config FRAMEBUFFER_VESA_MODE_113
265 bool "800x600 32k-color (1:5:5:5)"
267 config FRAMEBUFFER_VESA_MODE_114
268 bool "800x600 64k-color (5:6:5)"
270 config FRAMEBUFFER_VESA_MODE_115
271 bool "800x600 16.8M-color (8:8:8)"
273 config FRAMEBUFFER_VESA_MODE_116
274 bool "1024x768 32k-color (1:5:5:5)"
276 config FRAMEBUFFER_VESA_MODE_117
277 bool "1024x768 64k-color (5:6:5)"
279 config FRAMEBUFFER_VESA_MODE_118
280 bool "1024x768 16.8M-color (8:8:8)"
282 config FRAMEBUFFER_VESA_MODE_119
283 bool "1280x1024 32k-color (1:5:5:5)"
285 config FRAMEBUFFER_VESA_MODE_11A
286 bool "1280x1024 64k-color (5:6:5)"
288 config FRAMEBUFFER_VESA_MODE_11B
289 bool "1280x1024 16.8M-color (8:8:8)"
291 config FRAMEBUFFER_VESA_MODE_USER
292 bool "Manually select VESA mode"
296 # Map the config names to an integer (KB).
297 config FRAMEBUFFER_VESA_MODE
298 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
300 default 0x100 if FRAMEBUFFER_VESA_MODE_100
301 default 0x101 if FRAMEBUFFER_VESA_MODE_101
302 default 0x102 if FRAMEBUFFER_VESA_MODE_102
303 default 0x103 if FRAMEBUFFER_VESA_MODE_103
304 default 0x104 if FRAMEBUFFER_VESA_MODE_104
305 default 0x105 if FRAMEBUFFER_VESA_MODE_105
306 default 0x106 if FRAMEBUFFER_VESA_MODE_106
307 default 0x107 if FRAMEBUFFER_VESA_MODE_107
308 default 0x108 if FRAMEBUFFER_VESA_MODE_108
309 default 0x109 if FRAMEBUFFER_VESA_MODE_109
310 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
311 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
312 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
313 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
314 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
315 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
316 default 0x110 if FRAMEBUFFER_VESA_MODE_110
317 default 0x111 if FRAMEBUFFER_VESA_MODE_111
318 default 0x112 if FRAMEBUFFER_VESA_MODE_112
319 default 0x113 if FRAMEBUFFER_VESA_MODE_113
320 default 0x114 if FRAMEBUFFER_VESA_MODE_114
321 default 0x115 if FRAMEBUFFER_VESA_MODE_115
322 default 0x116 if FRAMEBUFFER_VESA_MODE_116
323 default 0x117 if FRAMEBUFFER_VESA_MODE_117
324 default 0x118 if FRAMEBUFFER_VESA_MODE_118
325 default 0x119 if FRAMEBUFFER_VESA_MODE_119
326 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
327 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
328 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
333 bool "Add an Firmware Support Package binary"
335 Select this option to add an Firmware Support Package binary to
336 the resulting U-Boot image. It is a binary blob which U-Boot uses
337 to set up SDRAM and other chipset specific initialization.
339 Note: Without this binary U-Boot will not be able to set up its
340 SDRAM so will not boot.
343 string "Firmware Support Package binary filename"
347 The filename of the file to use as Firmware Support Package binary
348 in the board directory.
351 hex "Firmware Support Package binary location"
355 FSP is not Position Independent Code (PIC) and the whole FSP has to
356 be rebased if it is placed at a location which is different from the
357 perferred base address specified during the FSP build. Use Intel's
358 Binary Configuration Tool (BCT) to do the rebase.
360 The default base address of 0xfffc0000 indicates that the binary must
361 be located at offset 0xc0000 from the beginning of a 1MB flash device.
363 config FSP_TEMP_RAM_ADDR
367 Stack top address which is used in FspInit after DRAM is ready and
370 config TSC_CALIBRATION_BYPASS
371 bool "Bypass Time-Stamp Counter (TSC) calibration"
374 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
375 running frequency via Model-Specific Register (MSR) and Programmable
376 Interval Timer (PIT). If the calibration does not work on your board,
377 select this option and provide a hardcoded TSC running frequency with
378 CONFIG_TSC_FREQ_IN_MHZ below.
380 Normally this option should be turned on in a simulation environment
383 config TSC_FREQ_IN_MHZ
384 int "Time-Stamp Counter (TSC) running frequency in MHz"
385 depends on TSC_CALIBRATION_BYPASS
388 The running frequency in MHz of Time-Stamp Counter (TSC).
392 config GENERATE_PIRQ_TABLE
393 bool "Generate a PIRQ table"
396 Generate a PIRQ routing table for this board. The PIRQ routing table
397 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
398 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
399 It specifies the interrupt router information as well how all the PCI
400 devices' interrupt pins are wired to PIRQs.
404 config MAX_PIRQ_LINKS
408 This variable specifies the number of PIRQ interrupt links which are
409 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
410 Some newer chipsets offer more than four links, commonly up to PIRQH.
412 config IRQ_SLOT_COUNT
416 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
417 which in turns forms a table of exact 4KiB. The default value 128
418 should be enough for most boards. If this does not fit your board,
419 change it according to your needs.
421 config PCIE_ECAM_BASE
425 This is the memory-mapped address of PCI configuration space, which
426 is only available through the Enhanced Configuration Access
427 Mechanism (ECAM) with PCI Express. It can be set up almost
428 anywhere. Before it is set up, it is possible to access PCI
429 configuration space through I/O access, but memory access is more
430 convenient. Using this, PCI can be scanned and configured. This
431 should be set to a region that does not conflict with memory
432 assigned to PCI devices - i.e. the memory and prefetch regions, as
433 passed to pci_set_region().
438 config BOOTSTAGE_REPORT