1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_COREBOOT
14 config VENDOR_EMULATION
25 # board-specific options below
26 source "board/coreboot/Kconfig"
27 source "board/emulation/Kconfig"
28 source "board/google/Kconfig"
29 source "board/intel/Kconfig"
31 # platform-specific options below
32 source "arch/x86/cpu/baytrail/Kconfig"
33 source "arch/x86/cpu/coreboot/Kconfig"
34 source "arch/x86/cpu/ivybridge/Kconfig"
35 source "arch/x86/cpu/qemu/Kconfig"
36 source "arch/x86/cpu/quark/Kconfig"
37 source "arch/x86/cpu/queensbay/Kconfig"
39 # architecture-specific options below
41 config SYS_MALLOC_F_LEN
50 depends on X86_RESET_VECTOR
59 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
68 config X86_RESET_VECTOR
72 config RESET_SEG_START
74 depends on X86_RESET_VECTOR
79 depends on X86_RESET_VECTOR
84 depends on X86_RESET_VECTOR
87 config SYS_X86_START16
89 depends on X86_RESET_VECTOR
92 config BOARD_ROMSIZE_KB_512
94 config BOARD_ROMSIZE_KB_1024
96 config BOARD_ROMSIZE_KB_2048
98 config BOARD_ROMSIZE_KB_4096
100 config BOARD_ROMSIZE_KB_8192
102 config BOARD_ROMSIZE_KB_16384
106 prompt "ROM chip size"
107 depends on X86_RESET_VECTOR
108 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
109 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
110 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
111 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
112 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
113 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
115 Select the size of the ROM chip you intend to flash U-Boot on.
117 The build system will take care of creating a u-boot.rom file
118 of the matching size.
120 config UBOOT_ROMSIZE_KB_512
123 Choose this option if you have a 512 KB ROM chip.
125 config UBOOT_ROMSIZE_KB_1024
126 bool "1024 KB (1 MB)"
128 Choose this option if you have a 1024 KB (1 MB) ROM chip.
130 config UBOOT_ROMSIZE_KB_2048
131 bool "2048 KB (2 MB)"
133 Choose this option if you have a 2048 KB (2 MB) ROM chip.
135 config UBOOT_ROMSIZE_KB_4096
136 bool "4096 KB (4 MB)"
138 Choose this option if you have a 4096 KB (4 MB) ROM chip.
140 config UBOOT_ROMSIZE_KB_8192
141 bool "8192 KB (8 MB)"
143 Choose this option if you have a 8192 KB (8 MB) ROM chip.
145 config UBOOT_ROMSIZE_KB_16384
146 bool "16384 KB (16 MB)"
148 Choose this option if you have a 16384 KB (16 MB) ROM chip.
152 # Map the config names to an integer (KB).
153 config UBOOT_ROMSIZE_KB
155 default 512 if UBOOT_ROMSIZE_KB_512
156 default 1024 if UBOOT_ROMSIZE_KB_1024
157 default 2048 if UBOOT_ROMSIZE_KB_2048
158 default 4096 if UBOOT_ROMSIZE_KB_4096
159 default 8192 if UBOOT_ROMSIZE_KB_8192
160 default 16384 if UBOOT_ROMSIZE_KB_16384
162 # Map the config names to a hex value (bytes).
165 default 0x80000 if UBOOT_ROMSIZE_KB_512
166 default 0x100000 if UBOOT_ROMSIZE_KB_1024
167 default 0x200000 if UBOOT_ROMSIZE_KB_2048
168 default 0x400000 if UBOOT_ROMSIZE_KB_4096
169 default 0x800000 if UBOOT_ROMSIZE_KB_8192
170 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
171 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
174 bool "Platform requires Intel Management Engine"
176 Newer higher-end devices have an Intel Management Engine (ME)
177 which is a very large binary blob (typically 1.5MB) which is
178 required for the platform to work. This enforces a particular
179 SPI flash format. You will need to supply the me.bin file in
180 your board directory.
183 bool "Perform a simple RAM test after SDRAM initialisation"
185 If there is something wrong with SDRAM then the platform will
186 often crash within U-Boot or the kernel. This option enables a
187 very simple RAM test that quickly checks whether the SDRAM seems
188 to work correctly. It is not exhaustive but can save time by
189 detecting obvious failures.
192 bool "Add an Firmware Support Package binary"
194 Select this option to add an Firmware Support Package binary to
195 the resulting U-Boot image. It is a binary blob which U-Boot uses
196 to set up SDRAM and other chipset specific initialization.
198 Note: Without this binary U-Boot will not be able to set up its
199 SDRAM so will not boot.
202 string "Firmware Support Package binary filename"
206 The filename of the file to use as Firmware Support Package binary
207 in the board directory.
210 hex "Firmware Support Package binary location"
214 FSP is not Position Independent Code (PIC) and the whole FSP has to
215 be rebased if it is placed at a location which is different from the
216 perferred base address specified during the FSP build. Use Intel's
217 Binary Configuration Tool (BCT) to do the rebase.
219 The default base address of 0xfffc0000 indicates that the binary must
220 be located at offset 0xc0000 from the beginning of a 1MB flash device.
222 config FSP_TEMP_RAM_ADDR
227 Stack top address which is used in FspInit after DRAM is ready and
231 bool "Enable Symmetric Multiprocessing"
234 Enable use of more than one CPU in U-Boot and the Operating System
235 when loaded. Each CPU will be started up and information can be
236 obtained using the 'cpu' command. If this option is disabled, then
237 only one CPU will be enabled regardless of the number of CPUs
241 int "Maximum number of CPUs permitted"
245 When using multi-CPU chips it is possible for U-Boot to start up
246 more than one CPU. The stack memory used by all of these CPUs is
247 pre-allocated so at present U-Boot wants to know the maximum
248 number of CPUs that may be present. Set this to at least as high
249 as the number of CPUs in your system (it uses about 4KB of RAM for
257 Each additional CPU started by U-Boot requires its own stack. This
258 option sets the stack size used by each CPU and directly affects
259 the memory used by this initialisation process. Typically 4KB is
262 config TSC_CALIBRATION_BYPASS
263 bool "Bypass Time-Stamp Counter (TSC) calibration"
266 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
267 running frequency via Model-Specific Register (MSR) and Programmable
268 Interval Timer (PIT). If the calibration does not work on your board,
269 select this option and provide a hardcoded TSC running frequency with
270 CONFIG_TSC_FREQ_IN_MHZ below.
272 Normally this option should be turned on in a simulation environment
275 config TSC_FREQ_IN_MHZ
276 int "Time-Stamp Counter (TSC) running frequency in MHz"
277 depends on TSC_CALIBRATION_BYPASS
280 The running frequency in MHz of Time-Stamp Counter (TSC).
283 bool "Add a VGA BIOS image"
285 Select this option if you have a VGA BIOS image that you would
286 like to add to your ROM.
289 string "VGA BIOS image filename"
290 depends on HAVE_VGA_BIOS
293 The filename of the VGA BIOS image in the board directory.
296 hex "VGA BIOS image location"
297 depends on HAVE_VGA_BIOS
300 The location of VGA BIOS image in the SPI flash. For example, base
301 address of 0xfff90000 indicates that the image will be put at offset
302 0x90000 from the beginning of a 1MB flash device.
306 config GENERATE_PIRQ_TABLE
307 bool "Generate a PIRQ table"
310 Generate a PIRQ routing table for this board. The PIRQ routing table
311 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
312 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
313 It specifies the interrupt router information as well how all the PCI
314 devices' interrupt pins are wired to PIRQs.
316 config GENERATE_SFI_TABLE
317 bool "Generate a SFI (Simple Firmware Interface) table"
319 The Simple Firmware Interface (SFI) provides a lightweight method
320 for platform firmware to pass information to the operating system
321 via static tables in memory. Kernel SFI support is required to
322 boot on SFI-only platforms. If you have ACPI tables then these are
325 U-Boot writes this table in write_sfi_table() just before booting
328 For more information, see http://simplefirmware.org
330 config GENERATE_MP_TABLE
331 bool "Generate an MP (Multi-Processor) table"
334 Generate an MP (Multi-Processor) table for this board. The MP table
335 provides a way for the operating system to support for symmetric
336 multiprocessing as well as symmetric I/O interrupt handling with
337 the local APIC and I/O APIC.
341 config MAX_PIRQ_LINKS
345 This variable specifies the number of PIRQ interrupt links which are
346 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
347 Some newer chipsets offer more than four links, commonly up to PIRQH.
349 config IRQ_SLOT_COUNT
353 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
354 which in turns forms a table of exact 4KiB. The default value 128
355 should be enough for most boards. If this does not fit your board,
356 change it according to your needs.
358 config PCIE_ECAM_BASE
362 This is the memory-mapped address of PCI configuration space, which
363 is only available through the Enhanced Configuration Access
364 Mechanism (ECAM) with PCI Express. It can be set up almost
365 anywhere. Before it is set up, it is possible to access PCI
366 configuration space through I/O access, but memory access is more
367 convenient. Using this, PCI can be scanned and configured. This
368 should be set to a region that does not conflict with memory
369 assigned to PCI devices - i.e. the memory and prefetch regions, as
370 passed to pci_set_region().
372 config PCIE_ECAM_SIZE
376 This is the size of memory-mapped address of PCI configuration space,
377 which is only available through the Enhanced Configuration Access
378 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
379 so a default 0x10000000 size covers all of the 256 buses which is the
380 maximum number of PCI buses as defined by the PCI specification.