1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
36 select SPL_SEPARATE_BSS
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
56 config VENDOR_ADVANTECH
59 config VENDOR_CONGATEC
62 config VENDOR_COREBOOT
71 config VENDOR_EMULATION
82 # subarchitectures-specific options below
84 bool "Intel MID platform support"
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
92 If you are building for a PC class system say N here.
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
98 # board-specific options below
99 source "board/advantech/Kconfig"
100 source "board/congatec/Kconfig"
101 source "board/coreboot/Kconfig"
102 source "board/dfi/Kconfig"
103 source "board/efi/Kconfig"
104 source "board/emulation/Kconfig"
105 source "board/google/Kconfig"
106 source "board/intel/Kconfig"
108 # platform-specific options below
109 source "arch/x86/cpu/apollolake/Kconfig"
110 source "arch/x86/cpu/baytrail/Kconfig"
111 source "arch/x86/cpu/braswell/Kconfig"
112 source "arch/x86/cpu/broadwell/Kconfig"
113 source "arch/x86/cpu/coreboot/Kconfig"
114 source "arch/x86/cpu/ivybridge/Kconfig"
115 source "arch/x86/cpu/efi/Kconfig"
116 source "arch/x86/cpu/qemu/Kconfig"
117 source "arch/x86/cpu/quark/Kconfig"
118 source "arch/x86/cpu/queensbay/Kconfig"
119 source "arch/x86/cpu/slimbootloader/Kconfig"
120 source "arch/x86/cpu/tangier/Kconfig"
122 # architecture-specific options below
127 config SYS_MALLOC_F_LEN
136 depends on X86_RESET_VECTOR
145 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
154 config X86_RESET_VECTOR
159 # The following options control where the 16-bit and 32-bit init lies
160 # If SPL is enabled then it normally holds this init code, and U-Boot proper
161 # is normally a 64-bit build.
163 # The 16-bit init refers to the reset vector and the small amount of code to
164 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
165 # or missing altogether if U-Boot is started from EFI or coreboot.
167 # The 32-bit init refers to processor init, running binary blobs including
168 # FSP, setting up interrupts and anything else that needs to be done in
169 # 32-bit code. It is normally in the same place as 16-bit init if that is
170 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
171 config X86_16BIT_INIT
173 depends on X86_RESET_VECTOR
174 default y if X86_RESET_VECTOR && !SPL
176 This is enabled when 16-bit init is in U-Boot proper
178 config SPL_X86_16BIT_INIT
180 depends on X86_RESET_VECTOR
181 default y if X86_RESET_VECTOR && SPL && !TPL
183 This is enabled when 16-bit init is in SPL
185 config TPL_X86_16BIT_INIT
187 depends on X86_RESET_VECTOR
188 default y if X86_RESET_VECTOR && TPL
190 This is enabled when 16-bit init is in TPL
192 config X86_32BIT_INIT
194 depends on X86_RESET_VECTOR
195 default y if X86_RESET_VECTOR && !SPL
197 This is enabled when 32-bit init is in U-Boot proper
199 config SPL_X86_32BIT_INIT
201 depends on X86_RESET_VECTOR
202 default y if X86_RESET_VECTOR && SPL
204 This is enabled when 32-bit init is in SPL
206 config RESET_SEG_START
208 depends on X86_RESET_VECTOR
213 depends on X86_RESET_VECTOR
216 config SYS_X86_START16
218 depends on X86_RESET_VECTOR
224 Enable inclusion of an Intel Firmware Interface Table (FIT) into the
225 image. This table is supposed to point to microcode and the like. So
226 far it is just a fixed table with the minimum set of headers, so that
227 it is actually present.
229 config X86_LOAD_FROM_32_BIT
230 bool "Boot from a 32-bit program"
232 Define this to boot U-Boot from a 32-bit program which sets
233 the GDT differently. This can be used to boot directly from
234 any stage of coreboot, for example, bypassing the normal
235 payload-loading feature.
237 config BOARD_ROMSIZE_KB_512
239 config BOARD_ROMSIZE_KB_1024
241 config BOARD_ROMSIZE_KB_2048
243 config BOARD_ROMSIZE_KB_4096
245 config BOARD_ROMSIZE_KB_8192
247 config BOARD_ROMSIZE_KB_16384
251 prompt "ROM chip size"
252 depends on X86_RESET_VECTOR
253 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
254 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
255 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
256 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
257 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
258 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
260 Select the size of the ROM chip you intend to flash U-Boot on.
262 The build system will take care of creating a u-boot.rom file
263 of the matching size.
265 config UBOOT_ROMSIZE_KB_512
268 Choose this option if you have a 512 KB ROM chip.
270 config UBOOT_ROMSIZE_KB_1024
271 bool "1024 KB (1 MB)"
273 Choose this option if you have a 1024 KB (1 MB) ROM chip.
275 config UBOOT_ROMSIZE_KB_2048
276 bool "2048 KB (2 MB)"
278 Choose this option if you have a 2048 KB (2 MB) ROM chip.
280 config UBOOT_ROMSIZE_KB_4096
281 bool "4096 KB (4 MB)"
283 Choose this option if you have a 4096 KB (4 MB) ROM chip.
285 config UBOOT_ROMSIZE_KB_8192
286 bool "8192 KB (8 MB)"
288 Choose this option if you have a 8192 KB (8 MB) ROM chip.
290 config UBOOT_ROMSIZE_KB_16384
291 bool "16384 KB (16 MB)"
293 Choose this option if you have a 16384 KB (16 MB) ROM chip.
297 # Map the config names to an integer (KB).
298 config UBOOT_ROMSIZE_KB
300 default 512 if UBOOT_ROMSIZE_KB_512
301 default 1024 if UBOOT_ROMSIZE_KB_1024
302 default 2048 if UBOOT_ROMSIZE_KB_2048
303 default 4096 if UBOOT_ROMSIZE_KB_4096
304 default 8192 if UBOOT_ROMSIZE_KB_8192
305 default 16384 if UBOOT_ROMSIZE_KB_16384
307 # Map the config names to a hex value (bytes).
310 default 0x80000 if UBOOT_ROMSIZE_KB_512
311 default 0x100000 if UBOOT_ROMSIZE_KB_1024
312 default 0x200000 if UBOOT_ROMSIZE_KB_2048
313 default 0x400000 if UBOOT_ROMSIZE_KB_4096
314 default 0x800000 if UBOOT_ROMSIZE_KB_8192
315 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
316 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
319 bool "Platform requires Intel Management Engine"
321 Newer higher-end devices have an Intel Management Engine (ME)
322 which is a very large binary blob (typically 1.5MB) which is
323 required for the platform to work. This enforces a particular
324 SPI flash format. You will need to supply the me.bin file in
325 your board directory.
328 bool "Perform a simple RAM test after SDRAM initialisation"
330 If there is something wrong with SDRAM then the platform will
331 often crash within U-Boot or the kernel. This option enables a
332 very simple RAM test that quickly checks whether the SDRAM seems
333 to work correctly. It is not exhaustive but can save time by
334 detecting obvious failures.
336 config FLASH_DESCRIPTOR_FILE
337 string "Flash descriptor binary filename"
338 depends on HAVE_INTEL_ME || FSP_VERSION2
339 default "descriptor.bin"
341 The filename of the file to use as flash descriptor in the
345 string "Intel Management Engine binary filename"
346 depends on HAVE_INTEL_ME
349 The filename of the file to use as Intel Management Engine in the
353 bool "Use HOB (Hand-Off Block)"
355 Select this option to access HOB (Hand-Off Block) data structures
356 and parse HOBs. This HOB infra structure can be reused with
357 different solutions across different platforms.
360 bool "Add an Firmware Support Package binary"
364 Select this option to add an Firmware Support Package binary to
365 the resulting U-Boot image. It is a binary blob which U-Boot uses
366 to set up SDRAM and other chipset specific initialization.
368 Note: Without this binary U-Boot will not be able to set up its
369 SDRAM so will not boot.
372 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
373 default y if !HAVE_FSP
375 Select this option if your board uses CAR init code, typically in a
376 car.S file, to get some initial memory for code execution. This is
377 common with Intel CPUs which don't use FSP.
384 Selects the FSP version to use. Intel has published several versions
385 of the FSP External Architecture Specification and this allows
386 selection of the version number used by a particular SoC.
389 bool "FSP version 1.x"
391 This covers versions 1.0 and 1.1a. See here for details:
392 https://github.com/IntelFsp/fsp/wiki
395 bool "FSP version 2.x"
397 This covers versions 2.0 and 2.1. See here for details:
398 https://github.com/IntelFsp/fsp/wiki
403 string "Firmware Support Package binary filename"
404 depends on FSP_VERSION1
407 The filename of the file to use as Firmware Support Package binary
408 in the board directory.
411 hex "Firmware Support Package binary location"
412 depends on FSP_VERSION1
415 FSP is not Position Independent Code (PIC) and the whole FSP has to
416 be rebased if it is placed at a location which is different from the
417 perferred base address specified during the FSP build. Use Intel's
418 Binary Configuration Tool (BCT) to do the rebase.
420 The default base address of 0xfffc0000 indicates that the binary must
421 be located at offset 0xc0000 from the beginning of a 1MB flash device.
426 string "Firmware Support Package binary filename (Temp RAM)"
429 The filename of the file to use for the temporary-RAM init phase from
430 the Firmware Support Package binary. Put this in the board directory.
431 It is used to set up an initial area of RAM which can be used for the
432 stack and other purposes, while bringing up the main system DRAM.
435 hex "Firmware Support Package binary location (Temp RAM)"
438 FSP is not Position-Independent Code (PIC) and FSP components have to
439 be rebased if placed at a location which is different from the
440 perferred base address specified during the FSP build. Use Intel's
441 Binary Configuration Tool (BCT) to do the rebase.
444 string "Firmware Support Package binary filename (Memory Init)"
447 The filename of the file to use for the RAM init phase from the
448 Firmware Support Package binary. Put this in the board directory.
449 It is used to set up the main system DRAM and runs in SPL, once
450 temporary RAM (CAR) is working.
453 string "Firmware Support Package binary filename (Silicon Init)"
456 The filename of the file to use for the Silicon init phase from the
457 Firmware Support Package binary. Put this in the board directory.
458 It is used to set up the silicon to work correctly and must be
459 executed after DRAM is running.
461 config IFWI_INPUT_FILE
462 string "Filename containing FIT (Firmware Interface Table) with IFWI"
463 default "fitimage.bin"
465 The IFWI is obtained by running a tool on this file to extract the
466 IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
467 microcode and other internal items.
471 config FSP_TEMP_RAM_ADDR
473 depends on FSP_VERSION1
476 Stack top address which is used in fsp_init() after DRAM is ready and
479 config FSP_SYS_MALLOC_F_LEN
481 depends on FSP_VERSION1
484 Additional size of malloc() pool before relocation.
488 depends on FSP_VERSION1
491 Most FSPs use UPD data region for some FSP customization. But there
492 are still some FSPs that might not even have UPD. For such FSPs,
493 override this to n in their platform Kconfig files.
495 config FSP_BROKEN_HOB
497 depends on FSP_VERSION1
499 Indicate some buggy FSPs that does not report memory used by FSP
500 itself as reserved in the resource descriptor HOB. Select this to
501 tell U-Boot to do some additional work to ensure U-Boot relocation
502 do not overwrite the important boot service data which is used by
503 FSP, otherwise the subsequent call to fsp_notify() will fail.
505 config ENABLE_MRC_CACHE
506 bool "Enable MRC cache"
507 depends on !EFI && !SYS_COREBOOT
509 Enable this feature to cause MRC data to be cached in NV storage
510 to be used for speeding up boot time on future reboots and/or
513 For platforms that use Intel FSP for the memory initialization,
514 please check FSP output HOB via U-Boot command 'fsp hob' to see
515 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
516 If such GUID does not exist, MRC cache is not available on such
517 platform (eg: Intel Queensbay), which means selecting this option
518 here does not make any difference.
521 bool "Add a System Agent binary"
524 Select this option to add a System Agent binary to
525 the resulting U-Boot image. MRC stands for Memory Reference Code.
526 It is a binary blob which U-Boot uses to set up SDRAM.
528 Note: Without this binary U-Boot will not be able to set up its
529 SDRAM so will not boot.
536 Enable caching for the memory reference code binary. This uses an
537 MTRR (memory type range register) to turn on caching for the section
538 of SPI flash that contains the memory reference code. This makes
539 SDRAM init run faster.
541 config CACHE_MRC_SIZE_KB
546 Sets the size of the cached area for the memory reference code.
547 This ends at the end of SPI flash (address 0xffffffff) and is
548 measured in KB. Typically this is set to 512, providing for 0.5MB
551 config DCACHE_RAM_BASE
555 Sets the base of the data cache area in memory space. This is the
556 start address of the cache-as-RAM (CAR) area and the address varies
557 depending on the CPU. Once CAR is set up, read/write memory becomes
558 available at this address and can be used temporarily until SDRAM
561 config DCACHE_RAM_SIZE
566 Sets the total size of the data cache area in memory space. This
567 sets the size of the cache-as-RAM (CAR) area. Note that much of the
568 CAR space is required by the MRC. The CAR space available to U-Boot
569 is normally at the start and typically extends to 1/4 or 1/2 of the
572 config DCACHE_RAM_MRC_VAR_SIZE
576 This is the amount of CAR (Cache as RAM) reserved for use by the
577 memory reference code. This depends on the implementation of the
578 memory reference code and must be set correctly or the board will
582 bool "Add a Reference Code binary"
584 Select this option to add a Reference Code binary to the resulting
585 U-Boot image. This is an Intel binary blob that handles system
586 initialisation, in this case the PCH and System Agent.
588 Note: Without this binary (on platforms that need it such as
589 broadwell) U-Boot will be missing some critical setup steps.
590 Various peripherals may fail to work.
592 config HAVE_MICROCODE
594 default y if !FSP_VERSION2
597 bool "Enable Symmetric Multiprocessing"
600 Enable use of more than one CPU in U-Boot and the Operating System
601 when loaded. Each CPU will be started up and information can be
602 obtained using the 'cpu' command. If this option is disabled, then
603 only one CPU will be enabled regardless of the number of CPUs
607 int "Maximum number of CPUs permitted"
611 When using multi-CPU chips it is possible for U-Boot to start up
612 more than one CPU. The stack memory used by all of these CPUs is
613 pre-allocated so at present U-Boot wants to know the maximum
614 number of CPUs that may be present. Set this to at least as high
615 as the number of CPUs in your system (it uses about 4KB of RAM for
623 Each additional CPU started by U-Boot requires its own stack. This
624 option sets the stack size used by each CPU and directly affects
625 the memory used by this initialisation process. Typically 4KB is
628 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
631 This option indicates that the turbo mode setting is not package
632 scoped. i.e. turbo_enable() needs to be called on not just the
633 bootstrap processor (BSP).
636 bool "Add a VGA BIOS image"
638 Select this option if you have a VGA BIOS image that you would
639 like to add to your ROM.
642 string "VGA BIOS image filename"
643 depends on HAVE_VGA_BIOS
646 The filename of the VGA BIOS image in the board directory.
649 hex "VGA BIOS image location"
650 depends on HAVE_VGA_BIOS
653 The location of VGA BIOS image in the SPI flash. For example, base
654 address of 0xfff90000 indicates that the image will be put at offset
655 0x90000 from the beginning of a 1MB flash device.
658 bool "Add a Video BIOS Table (VBT) image"
661 Select this option if you have a Video BIOS Table (VBT) image that
662 you would like to add to your ROM. This is normally required if you
663 are using an Intel FSP firmware that is complaint with spec 1.1 or
664 later to initialize the integrated graphics device (IGD).
666 Video BIOS Table, or VBT, provides platform and board specific
667 configuration information to the driver that is not discoverable
668 or available through other means. By other means the most used
669 method here is to read EDID table from the attached monitor, over
670 Display Data Channel (DDC) using two pin I2C serial interface. VBT
671 configuration is related to display hardware and is available via
672 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
675 string "Video BIOS Table (VBT) image filename"
679 The filename of the file to use as Video BIOS Table (VBT) image
680 in the board directory.
683 hex "Video BIOS Table (VBT) image location"
687 The location of Video BIOS Table (VBT) image in the SPI flash. For
688 example, base address of 0xfff90000 indicates that the image will
689 be put at offset 0x90000 from the beginning of a 1MB flash device.
692 bool "Enable FSP framebuffer driver support"
693 depends on HAVE_VBT && DM_VIDEO
695 Turn on this option to enable a framebuffer driver when U-Boot is
696 using Video BIOS Table (VBT) image for FSP firmware to initialize
697 the integrated graphics device.
699 config ROM_TABLE_ADDR
703 All x86 tables happen to like the address range from 0x0f0000
704 to 0x100000. We use 0xf0000 as the starting address to store
705 those tables, including PIRQ routing table, Multi-Processor
706 table and ACPI table.
708 config ROM_TABLE_SIZE
715 Select this to include the driver for the Interrupt Timer
716 Subsystem (ITSS) which is found on several Intel devices.
721 Select this to include the driver for the Primary to
722 Sideband Bridge (P2SB) which is found on several Intel
726 depends on !EFI && !SYS_COREBOOT
728 config GENERATE_PIRQ_TABLE
729 bool "Generate a PIRQ table"
732 Generate a PIRQ routing table for this board. The PIRQ routing table
733 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
734 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
735 It specifies the interrupt router information as well how all the PCI
736 devices' interrupt pins are wired to PIRQs.
738 config GENERATE_SFI_TABLE
739 bool "Generate a SFI (Simple Firmware Interface) table"
741 The Simple Firmware Interface (SFI) provides a lightweight method
742 for platform firmware to pass information to the operating system
743 via static tables in memory. Kernel SFI support is required to
744 boot on SFI-only platforms. If you have ACPI tables then these are
747 U-Boot writes this table in write_sfi_table() just before booting
750 For more information, see http://simplefirmware.org
752 config GENERATE_MP_TABLE
753 bool "Generate an MP (Multi-Processor) table"
756 Generate an MP (Multi-Processor) table for this board. The MP table
757 provides a way for the operating system to support for symmetric
758 multiprocessing as well as symmetric I/O interrupt handling with
759 the local APIC and I/O APIC.
761 config GENERATE_ACPI_TABLE
762 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
766 The Advanced Configuration and Power Interface (ACPI) specification
767 provides an open standard for device configuration and management
768 by the operating system. It defines platform-independent interfaces
769 for configuration and power management monitoring.
773 config HAVE_ACPI_RESUME
774 bool "Enable ACPI S3 resume"
775 select ENABLE_MRC_CACHE
777 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
778 state where all system context is lost except system memory. U-Boot
779 is responsible for restoring the machine state as it was before sleep.
780 It needs restore the memory controller, without overwriting memory
781 which is not marked as reserved. For the peripherals which lose their
782 registers, U-Boot needs to write the original value. When everything
783 is done, U-Boot needs to find out the wakeup vector provided by OSes
786 config S3_VGA_ROM_RUN
787 bool "Re-run VGA option ROMs on S3 resume"
788 depends on HAVE_ACPI_RESUME
790 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
791 this is needed when graphics console is being used in the kernel.
793 Turning it off can reduce some resume time, but be aware that your
794 graphics console won't work without VGA options ROMs. Set it to N
795 if your kernel is only on a serial console.
799 depends on HAVE_ACPI_RESUME
802 Estimated U-Boot's runtime stack size that needs to be reserved
803 during an ACPI S3 resume.
805 config MAX_PIRQ_LINKS
809 This variable specifies the number of PIRQ interrupt links which are
810 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
811 Some newer chipsets offer more than four links, commonly up to PIRQH.
813 config IRQ_SLOT_COUNT
817 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
818 which in turns forms a table of exact 4KiB. The default value 128
819 should be enough for most boards. If this does not fit your board,
820 change it according to your needs.
822 config PCIE_ECAM_BASE
826 This is the memory-mapped address of PCI configuration space, which
827 is only available through the Enhanced Configuration Access
828 Mechanism (ECAM) with PCI Express. It can be set up almost
829 anywhere. Before it is set up, it is possible to access PCI
830 configuration space through I/O access, but memory access is more
831 convenient. Using this, PCI can be scanned and configured. This
832 should be set to a region that does not conflict with memory
833 assigned to PCI devices - i.e. the memory and prefetch regions, as
834 passed to pci_set_region().
836 config PCIE_ECAM_SIZE
840 This is the size of memory-mapped address of PCI configuration space,
841 which is only available through the Enhanced Configuration Access
842 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
843 so a default 0x10000000 size covers all of the 256 buses which is the
844 maximum number of PCI buses as defined by the PCI specification.
847 bool "Enable Intel 8259 compatible interrupt controller"
850 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
851 slave) interrupt controllers. Include this to have U-Boot set up
852 the interrupt correctly.
855 bool "Enable Intel Advanced Programmable Interrupt Controller"
858 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
859 for catching interrupts and distributing them to one or more CPU
860 cores. In most cases there are some LAPICs (local) for each core and
861 one I/O APIC. This conjunction is found on most modern x86 systems.
866 Intel ICH6 compatible chipset pinctrl driver. It needs to work
867 together with the ICH6 compatible gpio driver.
873 Intel 8254 timer contains three counters which have fixed uses.
874 Include this to have U-Boot set up the timer correctly.
877 bool "Support booting SeaBIOS"
879 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
880 It can run in an emulator or natively on X86 hardware with the use
881 of coreboot/U-Boot. By turning on this option, U-Boot prepares
882 all the configuration tables that are necessary to boot SeaBIOS.
884 Check http://www.seabios.org/SeaBIOS for details.
886 config HIGH_TABLE_SIZE
887 hex "Size of configuration tables which reside in high memory"
891 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
892 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
893 puts a copy of configuration tables in high memory region which
894 is reserved on the stack before relocation. The region size is
895 determined by this option.
897 Increse it if the default size does not fit the board's needs.
898 This is most likely due to a large ACPI DSDT table is used.
900 config INTEL_CAR_CQOS
901 bool "Support Intel Cache Quality of Service"
903 Cache Quality of Service allows more fine-grained control of cache
904 usage. As result, it is possible to set up a portion of L2 cache for
905 CAR and use the remainder for actual caching.
908 # Each bit in QOS mask controls this many bytes. This is calculated as:
909 # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
911 config CACHE_QOS_SIZE_PER_BIT
913 depends on INTEL_CAR_CQOS
914 default 0x20000 # 128 KB
916 config X86_OFFSET_U_BOOT
917 hex "Offset of U-Boot in ROM image"
918 depends on HAVE_SYS_TEXT_BASE
919 default SYS_TEXT_BASE
921 config X86_OFFSET_SPL
922 hex "Offset of SPL in ROM image"
923 depends on SPL && X86
924 default SPL_TEXT_BASE
927 bool "Support ACPI general-purpose events"
929 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
930 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
931 needs access to these interrupts. This can happen when it uses a
932 peripheral that is set up to use GPEs and so cannot use the normal
933 GPIO mechanism for polling an input.
935 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
938 bool "Support ACPI general-purpose events in SPL"
940 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
941 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
942 needs access to these interrupts. This can happen when it uses a
943 peripheral that is set up to use GPEs and so cannot use the normal
944 GPIO mechanism for polling an input.
946 See https://queue.acm.org/blogposting.cfm?id=18977 for more info
949 bool "Support ACPI general-purpose events in TPL"
951 Enable a driver for ACPI GPEs to allow peripherals to send interrupts
952 via ACPI to the OS. In U-Boot this is only used when U-Boot itself
953 needs access to these interrupts. This can happen when it uses a
954 peripheral that is set up to use GPEs and so cannot use the normal
955 GPIO mechanism for polling an input.
957 See https://queue.acm.org/blogposting.cfm?id=18977 for more info