1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
36 select SPL_SEPARATE_BSS
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
56 config VENDOR_ADVANTECH
59 config VENDOR_CONGATEC
62 config VENDOR_COREBOOT
71 config VENDOR_EMULATION
82 # subarchitectures-specific options below
84 bool "Intel MID platform support"
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
92 If you are building for a PC class system say N here.
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
98 # board-specific options below
99 source "board/advantech/Kconfig"
100 source "board/congatec/Kconfig"
101 source "board/coreboot/Kconfig"
102 source "board/dfi/Kconfig"
103 source "board/efi/Kconfig"
104 source "board/emulation/Kconfig"
105 source "board/google/Kconfig"
106 source "board/intel/Kconfig"
108 # platform-specific options below
109 source "arch/x86/cpu/baytrail/Kconfig"
110 source "arch/x86/cpu/braswell/Kconfig"
111 source "arch/x86/cpu/broadwell/Kconfig"
112 source "arch/x86/cpu/coreboot/Kconfig"
113 source "arch/x86/cpu/ivybridge/Kconfig"
114 source "arch/x86/cpu/efi/Kconfig"
115 source "arch/x86/cpu/qemu/Kconfig"
116 source "arch/x86/cpu/quark/Kconfig"
117 source "arch/x86/cpu/queensbay/Kconfig"
118 source "arch/x86/cpu/tangier/Kconfig"
120 # architecture-specific options below
125 config SYS_MALLOC_F_LEN
134 depends on X86_RESET_VECTOR
143 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
152 config X86_RESET_VECTOR
157 # The following options control where the 16-bit and 32-bit init lies
158 # If SPL is enabled then it normally holds this init code, and U-Boot proper
159 # is normally a 64-bit build.
161 # The 16-bit init refers to the reset vector and the small amount of code to
162 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
163 # or missing altogether if U-Boot is started from EFI or coreboot.
165 # The 32-bit init refers to processor init, running binary blobs including
166 # FSP, setting up interrupts and anything else that needs to be done in
167 # 32-bit code. It is normally in the same place as 16-bit init if that is
168 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
169 config X86_16BIT_INIT
171 depends on X86_RESET_VECTOR
172 default y if X86_RESET_VECTOR && !SPL
174 This is enabled when 16-bit init is in U-Boot proper
176 config SPL_X86_16BIT_INIT
178 depends on X86_RESET_VECTOR
179 default y if X86_RESET_VECTOR && SPL && !TPL
181 This is enabled when 16-bit init is in SPL
183 config TPL_X86_16BIT_INIT
185 depends on X86_RESET_VECTOR
186 default y if X86_RESET_VECTOR && TPL
188 This is enabled when 16-bit init is in TPL
190 config X86_32BIT_INIT
192 depends on X86_RESET_VECTOR
193 default y if X86_RESET_VECTOR && !SPL
195 This is enabled when 32-bit init is in U-Boot proper
197 config SPL_X86_32BIT_INIT
199 depends on X86_RESET_VECTOR
200 default y if X86_RESET_VECTOR && SPL
202 This is enabled when 32-bit init is in SPL
204 config RESET_SEG_START
206 depends on X86_RESET_VECTOR
209 config RESET_SEG_SIZE
211 depends on X86_RESET_VECTOR
216 depends on X86_RESET_VECTOR
219 config SYS_X86_START16
221 depends on X86_RESET_VECTOR
224 config X86_LOAD_FROM_32_BIT
225 bool "Boot from a 32-bit program"
227 Define this to boot U-Boot from a 32-bit program which sets
228 the GDT differently. This can be used to boot directly from
229 any stage of coreboot, for example, bypassing the normal
230 payload-loading feature.
232 config BOARD_ROMSIZE_KB_512
234 config BOARD_ROMSIZE_KB_1024
236 config BOARD_ROMSIZE_KB_2048
238 config BOARD_ROMSIZE_KB_4096
240 config BOARD_ROMSIZE_KB_8192
242 config BOARD_ROMSIZE_KB_16384
246 prompt "ROM chip size"
247 depends on X86_RESET_VECTOR
248 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
249 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
250 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
251 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
252 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
253 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
255 Select the size of the ROM chip you intend to flash U-Boot on.
257 The build system will take care of creating a u-boot.rom file
258 of the matching size.
260 config UBOOT_ROMSIZE_KB_512
263 Choose this option if you have a 512 KB ROM chip.
265 config UBOOT_ROMSIZE_KB_1024
266 bool "1024 KB (1 MB)"
268 Choose this option if you have a 1024 KB (1 MB) ROM chip.
270 config UBOOT_ROMSIZE_KB_2048
271 bool "2048 KB (2 MB)"
273 Choose this option if you have a 2048 KB (2 MB) ROM chip.
275 config UBOOT_ROMSIZE_KB_4096
276 bool "4096 KB (4 MB)"
278 Choose this option if you have a 4096 KB (4 MB) ROM chip.
280 config UBOOT_ROMSIZE_KB_8192
281 bool "8192 KB (8 MB)"
283 Choose this option if you have a 8192 KB (8 MB) ROM chip.
285 config UBOOT_ROMSIZE_KB_16384
286 bool "16384 KB (16 MB)"
288 Choose this option if you have a 16384 KB (16 MB) ROM chip.
292 # Map the config names to an integer (KB).
293 config UBOOT_ROMSIZE_KB
295 default 512 if UBOOT_ROMSIZE_KB_512
296 default 1024 if UBOOT_ROMSIZE_KB_1024
297 default 2048 if UBOOT_ROMSIZE_KB_2048
298 default 4096 if UBOOT_ROMSIZE_KB_4096
299 default 8192 if UBOOT_ROMSIZE_KB_8192
300 default 16384 if UBOOT_ROMSIZE_KB_16384
302 # Map the config names to a hex value (bytes).
305 default 0x80000 if UBOOT_ROMSIZE_KB_512
306 default 0x100000 if UBOOT_ROMSIZE_KB_1024
307 default 0x200000 if UBOOT_ROMSIZE_KB_2048
308 default 0x400000 if UBOOT_ROMSIZE_KB_4096
309 default 0x800000 if UBOOT_ROMSIZE_KB_8192
310 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
311 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
314 bool "Platform requires Intel Management Engine"
316 Newer higher-end devices have an Intel Management Engine (ME)
317 which is a very large binary blob (typically 1.5MB) which is
318 required for the platform to work. This enforces a particular
319 SPI flash format. You will need to supply the me.bin file in
320 your board directory.
323 bool "Perform a simple RAM test after SDRAM initialisation"
325 If there is something wrong with SDRAM then the platform will
326 often crash within U-Boot or the kernel. This option enables a
327 very simple RAM test that quickly checks whether the SDRAM seems
328 to work correctly. It is not exhaustive but can save time by
329 detecting obvious failures.
331 config FLASH_DESCRIPTOR_FILE
332 string "Flash descriptor binary filename"
333 depends on HAVE_INTEL_ME
334 default "descriptor.bin"
336 The filename of the file to use as flash descriptor in the
340 string "Intel Management Engine binary filename"
341 depends on HAVE_INTEL_ME
344 The filename of the file to use as Intel Management Engine in the
348 bool "Add an Firmware Support Package binary"
351 Select this option to add an Firmware Support Package binary to
352 the resulting U-Boot image. It is a binary blob which U-Boot uses
353 to set up SDRAM and other chipset specific initialization.
355 Note: Without this binary U-Boot will not be able to set up its
356 SDRAM so will not boot.
359 string "Firmware Support Package binary filename"
363 The filename of the file to use as Firmware Support Package binary
364 in the board directory.
367 hex "Firmware Support Package binary location"
371 FSP is not Position Independent Code (PIC) and the whole FSP has to
372 be rebased if it is placed at a location which is different from the
373 perferred base address specified during the FSP build. Use Intel's
374 Binary Configuration Tool (BCT) to do the rebase.
376 The default base address of 0xfffc0000 indicates that the binary must
377 be located at offset 0xc0000 from the beginning of a 1MB flash device.
379 config FSP_TEMP_RAM_ADDR
384 Stack top address which is used in fsp_init() after DRAM is ready and
387 config FSP_SYS_MALLOC_F_LEN
392 Additional size of malloc() pool before relocation.
399 Most FSPs use UPD data region for some FSP customization. But there
400 are still some FSPs that might not even have UPD. For such FSPs,
401 override this to n in their platform Kconfig files.
403 config FSP_BROKEN_HOB
407 Indicate some buggy FSPs that does not report memory used by FSP
408 itself as reserved in the resource descriptor HOB. Select this to
409 tell U-Boot to do some additional work to ensure U-Boot relocation
410 do not overwrite the important boot service data which is used by
411 FSP, otherwise the subsequent call to fsp_notify() will fail.
413 config ENABLE_MRC_CACHE
414 bool "Enable MRC cache"
415 depends on !EFI && !SYS_COREBOOT
417 Enable this feature to cause MRC data to be cached in NV storage
418 to be used for speeding up boot time on future reboots and/or
421 For platforms that use Intel FSP for the memory initialization,
422 please check FSP output HOB via U-Boot command 'fsp hob' to see
423 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
424 If such GUID does not exist, MRC cache is not available on such
425 platform (eg: Intel Queensbay), which means selecting this option
426 here does not make any difference.
429 bool "Add a System Agent binary"
432 Select this option to add a System Agent binary to
433 the resulting U-Boot image. MRC stands for Memory Reference Code.
434 It is a binary blob which U-Boot uses to set up SDRAM.
436 Note: Without this binary U-Boot will not be able to set up its
437 SDRAM so will not boot.
444 Enable caching for the memory reference code binary. This uses an
445 MTRR (memory type range register) to turn on caching for the section
446 of SPI flash that contains the memory reference code. This makes
447 SDRAM init run faster.
449 config CACHE_MRC_SIZE_KB
454 Sets the size of the cached area for the memory reference code.
455 This ends at the end of SPI flash (address 0xffffffff) and is
456 measured in KB. Typically this is set to 512, providing for 0.5MB
459 config DCACHE_RAM_BASE
463 Sets the base of the data cache area in memory space. This is the
464 start address of the cache-as-RAM (CAR) area and the address varies
465 depending on the CPU. Once CAR is set up, read/write memory becomes
466 available at this address and can be used temporarily until SDRAM
469 config DCACHE_RAM_SIZE
474 Sets the total size of the data cache area in memory space. This
475 sets the size of the cache-as-RAM (CAR) area. Note that much of the
476 CAR space is required by the MRC. The CAR space available to U-Boot
477 is normally at the start and typically extends to 1/4 or 1/2 of the
480 config DCACHE_RAM_MRC_VAR_SIZE
484 This is the amount of CAR (Cache as RAM) reserved for use by the
485 memory reference code. This depends on the implementation of the
486 memory reference code and must be set correctly or the board will
490 bool "Add a Reference Code binary"
492 Select this option to add a Reference Code binary to the resulting
493 U-Boot image. This is an Intel binary blob that handles system
494 initialisation, in this case the PCH and System Agent.
496 Note: Without this binary (on platforms that need it such as
497 broadwell) U-Boot will be missing some critical setup steps.
498 Various peripherals may fail to work.
501 bool "Enable Symmetric Multiprocessing"
504 Enable use of more than one CPU in U-Boot and the Operating System
505 when loaded. Each CPU will be started up and information can be
506 obtained using the 'cpu' command. If this option is disabled, then
507 only one CPU will be enabled regardless of the number of CPUs
511 int "Maximum number of CPUs permitted"
515 When using multi-CPU chips it is possible for U-Boot to start up
516 more than one CPU. The stack memory used by all of these CPUs is
517 pre-allocated so at present U-Boot wants to know the maximum
518 number of CPUs that may be present. Set this to at least as high
519 as the number of CPUs in your system (it uses about 4KB of RAM for
527 Each additional CPU started by U-Boot requires its own stack. This
528 option sets the stack size used by each CPU and directly affects
529 the memory used by this initialisation process. Typically 4KB is
532 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
535 This option indicates that the turbo mode setting is not package
536 scoped. i.e. turbo_enable() needs to be called on not just the
537 bootstrap processor (BSP).
540 bool "Add a VGA BIOS image"
542 Select this option if you have a VGA BIOS image that you would
543 like to add to your ROM.
546 string "VGA BIOS image filename"
547 depends on HAVE_VGA_BIOS
550 The filename of the VGA BIOS image in the board directory.
553 hex "VGA BIOS image location"
554 depends on HAVE_VGA_BIOS
557 The location of VGA BIOS image in the SPI flash. For example, base
558 address of 0xfff90000 indicates that the image will be put at offset
559 0x90000 from the beginning of a 1MB flash device.
562 bool "Add a Video BIOS Table (VBT) image"
565 Select this option if you have a Video BIOS Table (VBT) image that
566 you would like to add to your ROM. This is normally required if you
567 are using an Intel FSP firmware that is complaint with spec 1.1 or
568 later to initialize the integrated graphics device (IGD).
570 Video BIOS Table, or VBT, provides platform and board specific
571 configuration information to the driver that is not discoverable
572 or available through other means. By other means the most used
573 method here is to read EDID table from the attached monitor, over
574 Display Data Channel (DDC) using two pin I2C serial interface. VBT
575 configuration is related to display hardware and is available via
576 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
579 string "Video BIOS Table (VBT) image filename"
583 The filename of the file to use as Video BIOS Table (VBT) image
584 in the board directory.
587 hex "Video BIOS Table (VBT) image location"
591 The location of Video BIOS Table (VBT) image in the SPI flash. For
592 example, base address of 0xfff90000 indicates that the image will
593 be put at offset 0x90000 from the beginning of a 1MB flash device.
596 bool "Enable FSP framebuffer driver support"
597 depends on HAVE_VBT && DM_VIDEO
599 Turn on this option to enable a framebuffer driver when U-Boot is
600 using Video BIOS Table (VBT) image for FSP firmware to initialize
601 the integrated graphics device.
603 config ROM_TABLE_ADDR
607 All x86 tables happen to like the address range from 0x0f0000
608 to 0x100000. We use 0xf0000 as the starting address to store
609 those tables, including PIRQ routing table, Multi-Processor
610 table and ACPI table.
612 config ROM_TABLE_SIZE
617 depends on !EFI && !SYS_COREBOOT
619 config GENERATE_PIRQ_TABLE
620 bool "Generate a PIRQ table"
623 Generate a PIRQ routing table for this board. The PIRQ routing table
624 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
625 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
626 It specifies the interrupt router information as well how all the PCI
627 devices' interrupt pins are wired to PIRQs.
629 config GENERATE_SFI_TABLE
630 bool "Generate a SFI (Simple Firmware Interface) table"
632 The Simple Firmware Interface (SFI) provides a lightweight method
633 for platform firmware to pass information to the operating system
634 via static tables in memory. Kernel SFI support is required to
635 boot on SFI-only platforms. If you have ACPI tables then these are
638 U-Boot writes this table in write_sfi_table() just before booting
641 For more information, see http://simplefirmware.org
643 config GENERATE_MP_TABLE
644 bool "Generate an MP (Multi-Processor) table"
647 Generate an MP (Multi-Processor) table for this board. The MP table
648 provides a way for the operating system to support for symmetric
649 multiprocessing as well as symmetric I/O interrupt handling with
650 the local APIC and I/O APIC.
652 config GENERATE_ACPI_TABLE
653 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
657 The Advanced Configuration and Power Interface (ACPI) specification
658 provides an open standard for device configuration and management
659 by the operating system. It defines platform-independent interfaces
660 for configuration and power management monitoring.
664 config HAVE_ACPI_RESUME
665 bool "Enable ACPI S3 resume"
666 select ENABLE_MRC_CACHE
668 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
669 state where all system context is lost except system memory. U-Boot
670 is responsible for restoring the machine state as it was before sleep.
671 It needs restore the memory controller, without overwriting memory
672 which is not marked as reserved. For the peripherals which lose their
673 registers, U-Boot needs to write the original value. When everything
674 is done, U-Boot needs to find out the wakeup vector provided by OSes
677 config S3_VGA_ROM_RUN
678 bool "Re-run VGA option ROMs on S3 resume"
679 depends on HAVE_ACPI_RESUME
681 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
682 this is needed when graphics console is being used in the kernel.
684 Turning it off can reduce some resume time, but be aware that your
685 graphics console won't work without VGA options ROMs. Set it to N
686 if your kernel is only on a serial console.
690 depends on HAVE_ACPI_RESUME
693 Estimated U-Boot's runtime stack size that needs to be reserved
694 during an ACPI S3 resume.
696 config MAX_PIRQ_LINKS
700 This variable specifies the number of PIRQ interrupt links which are
701 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
702 Some newer chipsets offer more than four links, commonly up to PIRQH.
704 config IRQ_SLOT_COUNT
708 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
709 which in turns forms a table of exact 4KiB. The default value 128
710 should be enough for most boards. If this does not fit your board,
711 change it according to your needs.
713 config PCIE_ECAM_BASE
717 This is the memory-mapped address of PCI configuration space, which
718 is only available through the Enhanced Configuration Access
719 Mechanism (ECAM) with PCI Express. It can be set up almost
720 anywhere. Before it is set up, it is possible to access PCI
721 configuration space through I/O access, but memory access is more
722 convenient. Using this, PCI can be scanned and configured. This
723 should be set to a region that does not conflict with memory
724 assigned to PCI devices - i.e. the memory and prefetch regions, as
725 passed to pci_set_region().
727 config PCIE_ECAM_SIZE
731 This is the size of memory-mapped address of PCI configuration space,
732 which is only available through the Enhanced Configuration Access
733 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
734 so a default 0x10000000 size covers all of the 256 buses which is the
735 maximum number of PCI buses as defined by the PCI specification.
738 bool "Enable Intel 8259 compatible interrupt controller"
741 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
742 slave) interrupt controllers. Include this to have U-Boot set up
743 the interrupt correctly.
746 bool "Enable Intel Advanced Programmable Interrupt Controller"
749 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
750 for catching interrupts and distributing them to one or more CPU
751 cores. In most cases there are some LAPICs (local) for each core and
752 one I/O APIC. This conjunction is found on most modern x86 systems.
757 Intel ICH6 compatible chipset pinctrl driver. It needs to work
758 together with the ICH6 compatible gpio driver.
764 Intel 8254 timer contains three counters which have fixed uses.
765 Include this to have U-Boot set up the timer correctly.
768 bool "Support booting SeaBIOS"
770 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
771 It can run in an emulator or natively on X86 hardware with the use
772 of coreboot/U-Boot. By turning on this option, U-Boot prepares
773 all the configuration tables that are necessary to boot SeaBIOS.
775 Check http://www.seabios.org/SeaBIOS for details.
777 config HIGH_TABLE_SIZE
778 hex "Size of configuration tables which reside in high memory"
782 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
783 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
784 puts a copy of configuration tables in high memory region which
785 is reserved on the stack before relocation. The region size is
786 determined by this option.
788 Increse it if the default size does not fit the board's needs.
789 This is most likely due to a large ACPI DSDT table is used.