1 menu "x86 architecture"
8 prompt "Mainboard vendor"
9 default VENDOR_EMULATION
11 config VENDOR_CONGATEC
14 config VENDOR_COREBOOT
20 config VENDOR_EMULATION
31 # board-specific options below
32 source "board/congatec/Kconfig"
33 source "board/coreboot/Kconfig"
34 source "board/efi/Kconfig"
35 source "board/emulation/Kconfig"
36 source "board/google/Kconfig"
37 source "board/intel/Kconfig"
39 # platform-specific options below
40 source "arch/x86/cpu/baytrail/Kconfig"
41 source "arch/x86/cpu/broadwell/Kconfig"
42 source "arch/x86/cpu/coreboot/Kconfig"
43 source "arch/x86/cpu/ivybridge/Kconfig"
44 source "arch/x86/cpu/qemu/Kconfig"
45 source "arch/x86/cpu/quark/Kconfig"
46 source "arch/x86/cpu/queensbay/Kconfig"
48 # architecture-specific options below
53 config SYS_MALLOC_F_LEN
62 depends on X86_RESET_VECTOR
71 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
80 config X86_RESET_VECTOR
84 config RESET_SEG_START
86 depends on X86_RESET_VECTOR
91 depends on X86_RESET_VECTOR
96 depends on X86_RESET_VECTOR
99 config SYS_X86_START16
101 depends on X86_RESET_VECTOR
104 config BOARD_ROMSIZE_KB_512
106 config BOARD_ROMSIZE_KB_1024
108 config BOARD_ROMSIZE_KB_2048
110 config BOARD_ROMSIZE_KB_4096
112 config BOARD_ROMSIZE_KB_8192
114 config BOARD_ROMSIZE_KB_16384
118 prompt "ROM chip size"
119 depends on X86_RESET_VECTOR
120 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
121 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
122 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
123 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
124 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
125 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
127 Select the size of the ROM chip you intend to flash U-Boot on.
129 The build system will take care of creating a u-boot.rom file
130 of the matching size.
132 config UBOOT_ROMSIZE_KB_512
135 Choose this option if you have a 512 KB ROM chip.
137 config UBOOT_ROMSIZE_KB_1024
138 bool "1024 KB (1 MB)"
140 Choose this option if you have a 1024 KB (1 MB) ROM chip.
142 config UBOOT_ROMSIZE_KB_2048
143 bool "2048 KB (2 MB)"
145 Choose this option if you have a 2048 KB (2 MB) ROM chip.
147 config UBOOT_ROMSIZE_KB_4096
148 bool "4096 KB (4 MB)"
150 Choose this option if you have a 4096 KB (4 MB) ROM chip.
152 config UBOOT_ROMSIZE_KB_8192
153 bool "8192 KB (8 MB)"
155 Choose this option if you have a 8192 KB (8 MB) ROM chip.
157 config UBOOT_ROMSIZE_KB_16384
158 bool "16384 KB (16 MB)"
160 Choose this option if you have a 16384 KB (16 MB) ROM chip.
164 # Map the config names to an integer (KB).
165 config UBOOT_ROMSIZE_KB
167 default 512 if UBOOT_ROMSIZE_KB_512
168 default 1024 if UBOOT_ROMSIZE_KB_1024
169 default 2048 if UBOOT_ROMSIZE_KB_2048
170 default 4096 if UBOOT_ROMSIZE_KB_4096
171 default 8192 if UBOOT_ROMSIZE_KB_8192
172 default 16384 if UBOOT_ROMSIZE_KB_16384
174 # Map the config names to a hex value (bytes).
177 default 0x80000 if UBOOT_ROMSIZE_KB_512
178 default 0x100000 if UBOOT_ROMSIZE_KB_1024
179 default 0x200000 if UBOOT_ROMSIZE_KB_2048
180 default 0x400000 if UBOOT_ROMSIZE_KB_4096
181 default 0x800000 if UBOOT_ROMSIZE_KB_8192
182 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
183 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
186 bool "Platform requires Intel Management Engine"
188 Newer higher-end devices have an Intel Management Engine (ME)
189 which is a very large binary blob (typically 1.5MB) which is
190 required for the platform to work. This enforces a particular
191 SPI flash format. You will need to supply the me.bin file in
192 your board directory.
195 bool "Perform a simple RAM test after SDRAM initialisation"
197 If there is something wrong with SDRAM then the platform will
198 often crash within U-Boot or the kernel. This option enables a
199 very simple RAM test that quickly checks whether the SDRAM seems
200 to work correctly. It is not exhaustive but can save time by
201 detecting obvious failures.
204 bool "Add an Firmware Support Package binary"
207 Select this option to add an Firmware Support Package binary to
208 the resulting U-Boot image. It is a binary blob which U-Boot uses
209 to set up SDRAM and other chipset specific initialization.
211 Note: Without this binary U-Boot will not be able to set up its
212 SDRAM so will not boot.
215 string "Firmware Support Package binary filename"
219 The filename of the file to use as Firmware Support Package binary
220 in the board directory.
223 hex "Firmware Support Package binary location"
227 FSP is not Position Independent Code (PIC) and the whole FSP has to
228 be rebased if it is placed at a location which is different from the
229 perferred base address specified during the FSP build. Use Intel's
230 Binary Configuration Tool (BCT) to do the rebase.
232 The default base address of 0xfffc0000 indicates that the binary must
233 be located at offset 0xc0000 from the beginning of a 1MB flash device.
235 config FSP_TEMP_RAM_ADDR
240 Stack top address which is used in fsp_init() after DRAM is ready and
243 config FSP_SYS_MALLOC_F_LEN
248 Additional size of malloc() pool before relocation.
255 Most FSPs use UPD data region for some FSP customization. But there
256 are still some FSPs that might not even have UPD. For such FSPs,
257 override this to n in their platform Kconfig files.
259 config FSP_BROKEN_HOB
263 Indicate some buggy FSPs that does not report memory used by FSP
264 itself as reserved in the resource descriptor HOB. Select this to
265 tell U-Boot to do some additional work to ensure U-Boot relocation
266 do not overwrite the important boot service data which is used by
267 FSP, otherwise the subsequent call to fsp_notify() will fail.
269 config ENABLE_MRC_CACHE
270 bool "Enable MRC cache"
271 depends on !EFI && !SYS_COREBOOT
273 Enable this feature to cause MRC data to be cached in NV storage
274 to be used for speeding up boot time on future reboots and/or
277 For platforms that use Intel FSP for the memory initialization,
278 please check FSP output HOB via U-Boot command 'fsp hob' to see
279 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
280 If such GUID does not exist, MRC cache is not avaiable on such
281 platform (eg: Intel Queensbay), which means selecting this option
282 here does not make any difference.
285 bool "Add a System Agent binary"
288 Select this option to add a System Agent binary to
289 the resulting U-Boot image. MRC stands for Memory Reference Code.
290 It is a binary blob which U-Boot uses to set up SDRAM.
292 Note: Without this binary U-Boot will not be able to set up its
293 SDRAM so will not boot.
300 Enable caching for the memory reference code binary. This uses an
301 MTRR (memory type range register) to turn on caching for the section
302 of SPI flash that contains the memory reference code. This makes
303 SDRAM init run faster.
305 config CACHE_MRC_SIZE_KB
310 Sets the size of the cached area for the memory reference code.
311 This ends at the end of SPI flash (address 0xffffffff) and is
312 measured in KB. Typically this is set to 512, providing for 0.5MB
315 config DCACHE_RAM_BASE
319 Sets the base of the data cache area in memory space. This is the
320 start address of the cache-as-RAM (CAR) area and the address varies
321 depending on the CPU. Once CAR is set up, read/write memory becomes
322 available at this address and can be used temporarily until SDRAM
325 config DCACHE_RAM_SIZE
330 Sets the total size of the data cache area in memory space. This
331 sets the size of the cache-as-RAM (CAR) area. Note that much of the
332 CAR space is required by the MRC. The CAR space available to U-Boot
333 is normally at the start and typically extends to 1/4 or 1/2 of the
336 config DCACHE_RAM_MRC_VAR_SIZE
340 This is the amount of CAR (Cache as RAM) reserved for use by the
341 memory reference code. This depends on the implementation of the
342 memory reference code and must be set correctly or the board will
346 bool "Add a Reference Code binary"
348 Select this option to add a Reference Code binary to the resulting
349 U-Boot image. This is an Intel binary blob that handles system
350 initialisation, in this case the PCH and System Agent.
352 Note: Without this binary (on platforms that need it such as
353 broadwell) U-Boot will be missing some critical setup steps.
354 Various peripherals may fail to work.
357 bool "Enable Symmetric Multiprocessing"
360 Enable use of more than one CPU in U-Boot and the Operating System
361 when loaded. Each CPU will be started up and information can be
362 obtained using the 'cpu' command. If this option is disabled, then
363 only one CPU will be enabled regardless of the number of CPUs
367 int "Maximum number of CPUs permitted"
371 When using multi-CPU chips it is possible for U-Boot to start up
372 more than one CPU. The stack memory used by all of these CPUs is
373 pre-allocated so at present U-Boot wants to know the maximum
374 number of CPUs that may be present. Set this to at least as high
375 as the number of CPUs in your system (it uses about 4KB of RAM for
383 Each additional CPU started by U-Boot requires its own stack. This
384 option sets the stack size used by each CPU and directly affects
385 the memory used by this initialisation process. Typically 4KB is
389 bool "Add a VGA BIOS image"
391 Select this option if you have a VGA BIOS image that you would
392 like to add to your ROM.
395 string "VGA BIOS image filename"
396 depends on HAVE_VGA_BIOS
399 The filename of the VGA BIOS image in the board directory.
402 hex "VGA BIOS image location"
403 depends on HAVE_VGA_BIOS
406 The location of VGA BIOS image in the SPI flash. For example, base
407 address of 0xfff90000 indicates that the image will be put at offset
408 0x90000 from the beginning of a 1MB flash device.
411 depends on !EFI && !SYS_COREBOOT
413 config GENERATE_PIRQ_TABLE
414 bool "Generate a PIRQ table"
417 Generate a PIRQ routing table for this board. The PIRQ routing table
418 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
419 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
420 It specifies the interrupt router information as well how all the PCI
421 devices' interrupt pins are wired to PIRQs.
423 config GENERATE_SFI_TABLE
424 bool "Generate a SFI (Simple Firmware Interface) table"
426 The Simple Firmware Interface (SFI) provides a lightweight method
427 for platform firmware to pass information to the operating system
428 via static tables in memory. Kernel SFI support is required to
429 boot on SFI-only platforms. If you have ACPI tables then these are
432 U-Boot writes this table in write_sfi_table() just before booting
435 For more information, see http://simplefirmware.org
437 config GENERATE_MP_TABLE
438 bool "Generate an MP (Multi-Processor) table"
441 Generate an MP (Multi-Processor) table for this board. The MP table
442 provides a way for the operating system to support for symmetric
443 multiprocessing as well as symmetric I/O interrupt handling with
444 the local APIC and I/O APIC.
446 config GENERATE_ACPI_TABLE
447 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
451 The Advanced Configuration and Power Interface (ACPI) specification
452 provides an open standard for device configuration and management
453 by the operating system. It defines platform-independent interfaces
454 for configuration and power management monitoring.
456 config GENERATE_SMBIOS_TABLE
457 bool "Generate an SMBIOS (System Management BIOS) table"
460 The System Management BIOS (SMBIOS) specification addresses how
461 motherboard and system vendors present management information about
462 their products in a standard format by extending the BIOS interface
463 on Intel architecture systems.
465 Check http://www.dmtf.org/standards/smbios for details.
469 config MAX_PIRQ_LINKS
473 This variable specifies the number of PIRQ interrupt links which are
474 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
475 Some newer chipsets offer more than four links, commonly up to PIRQH.
477 config IRQ_SLOT_COUNT
481 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
482 which in turns forms a table of exact 4KiB. The default value 128
483 should be enough for most boards. If this does not fit your board,
484 change it according to your needs.
486 config PCIE_ECAM_BASE
490 This is the memory-mapped address of PCI configuration space, which
491 is only available through the Enhanced Configuration Access
492 Mechanism (ECAM) with PCI Express. It can be set up almost
493 anywhere. Before it is set up, it is possible to access PCI
494 configuration space through I/O access, but memory access is more
495 convenient. Using this, PCI can be scanned and configured. This
496 should be set to a region that does not conflict with memory
497 assigned to PCI devices - i.e. the memory and prefetch regions, as
498 passed to pci_set_region().
500 config PCIE_ECAM_SIZE
504 This is the size of memory-mapped address of PCI configuration space,
505 which is only available through the Enhanced Configuration Access
506 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
507 so a default 0x10000000 size covers all of the 256 buses which is the
508 maximum number of PCI buses as defined by the PCI specification.
514 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
515 slave) interrupt controllers. Include this to have U-Boot set up
516 the interrupt correctly.
522 Intel 8254 timer contains three counters which have fixed uses.
523 Include this to have U-Boot set up the timer correctly.
532 bool "Support booting SeaBIOS"
534 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
535 It can run in an emulator or natively on X86 hardware with the use
536 of coreboot/U-Boot. By turning on this option, U-Boot prepares
537 all the configuration tables that are necessary to boot SeaBIOS.
539 Check http://www.seabios.org/SeaBIOS for details.
541 config HIGH_TABLE_SIZE
542 hex "Size of configuration tables which reside in high memory"
546 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
547 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
548 puts a copy of configuration tables in high memory region which
549 is reserved on the stack before relocation. The region size is
550 determined by this option.
552 Increse it if the default size does not fit the board's needs.
553 This is most likely due to a large ACPI DSDT table is used.
555 source "arch/x86/lib/efi/Kconfig"