1 menu "x86 architecture"
7 config USE_PRIVATE_LIBGCC
11 prompt "Target select"
13 config TARGET_COREBOOT
14 bool "Support coreboot"
16 This target is used for running U-Boot on top of Coreboot. In
17 this case Coreboot does the early inititalisation, and U-Boot
18 takes over once the RAM, video and CPU are fully running.
19 U-Boot is loaded as a fallback payload from Coreboot, in
20 Coreboot terminology. This method was used for the Chromebook
23 config TARGET_CHROMEBOOK_LINK
24 bool "Support Chromebook link"
26 This is the Chromebook Pixel released in 2013. It uses an Intel
27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
28 SDRAM. It has a Panther Point platform controller hub, PCIe
29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD
30 reader, microphone and speakers, display port and 32GB SATA
31 solid state drive. There is a Chrome OS EC connected on LPC,
32 and it provides a 2560x1700 high resolution touch-enabled LCD
35 config TARGET_CROWNBAY
36 bool "Support Intel Crown Bay CRB"
38 This is the Intel Crown Bay Customer Reference Board. It contains
39 the Intel Atom Processor E6xx populated on the COM Express module
40 with 1GB DDR2 soldered down memory and a carrier board with the
41 Intel Platform Controller Hub EG20T, other system components and
42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
44 config TARGET_MINNOWMAX
45 bool "Support Intel Minnowboard MAX"
47 This is the Intel Minnowboard MAX. It contains an Atom E3800
48 processor in a small form factor with Ethernet, micro-SD, USB 2,
49 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
50 It requires some binary blobs - see README.x86 for details.
52 Note that PCIE_ECAM_BASE is set up by the FSP so the value used
53 by U-Boot matches that value.
56 bool "Support Intel Galileo"
58 This is the Intel Galileo board, which is the first in a family of
59 Arduino-certified development and prototyping boards based on Intel
60 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
61 single-core, single-thread, Intel Pentium processor instrunction set
62 architecture (ISA) compatible, operating at speeds up to 400Mhz,
63 along with 256MB DDR3 memory. It supports a wide range of industry
64 standard I/O interfaces, including a full-sized mini-PCIe slot,
65 one 100Mb Ethernet port, a microSD card slot, a USB host port and
82 config SYS_MALLOC_F_LEN
91 depends on X86_RESET_VECTOR
100 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
109 config X86_RESET_VECTOR
113 config SYS_X86_START16
115 depends on X86_RESET_VECTOR
118 config BOARD_ROMSIZE_KB_512
120 config BOARD_ROMSIZE_KB_1024
122 config BOARD_ROMSIZE_KB_2048
124 config BOARD_ROMSIZE_KB_4096
126 config BOARD_ROMSIZE_KB_8192
128 config BOARD_ROMSIZE_KB_16384
132 prompt "ROM chip size"
133 depends on X86_RESET_VECTOR
134 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
135 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
136 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
137 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
138 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
139 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
141 Select the size of the ROM chip you intend to flash U-Boot on.
143 The build system will take care of creating a u-boot.rom file
144 of the matching size.
146 config UBOOT_ROMSIZE_KB_512
149 Choose this option if you have a 512 KB ROM chip.
151 config UBOOT_ROMSIZE_KB_1024
152 bool "1024 KB (1 MB)"
154 Choose this option if you have a 1024 KB (1 MB) ROM chip.
156 config UBOOT_ROMSIZE_KB_2048
157 bool "2048 KB (2 MB)"
159 Choose this option if you have a 2048 KB (2 MB) ROM chip.
161 config UBOOT_ROMSIZE_KB_4096
162 bool "4096 KB (4 MB)"
164 Choose this option if you have a 4096 KB (4 MB) ROM chip.
166 config UBOOT_ROMSIZE_KB_8192
167 bool "8192 KB (8 MB)"
169 Choose this option if you have a 8192 KB (8 MB) ROM chip.
171 config UBOOT_ROMSIZE_KB_16384
172 bool "16384 KB (16 MB)"
174 Choose this option if you have a 16384 KB (16 MB) ROM chip.
178 # Map the config names to an integer (KB).
179 config UBOOT_ROMSIZE_KB
181 default 512 if UBOOT_ROMSIZE_KB_512
182 default 1024 if UBOOT_ROMSIZE_KB_1024
183 default 2048 if UBOOT_ROMSIZE_KB_2048
184 default 4096 if UBOOT_ROMSIZE_KB_4096
185 default 8192 if UBOOT_ROMSIZE_KB_8192
186 default 16384 if UBOOT_ROMSIZE_KB_16384
188 # Map the config names to a hex value (bytes).
191 default 0x80000 if UBOOT_ROMSIZE_KB_512
192 default 0x100000 if UBOOT_ROMSIZE_KB_1024
193 default 0x200000 if UBOOT_ROMSIZE_KB_2048
194 default 0x400000 if UBOOT_ROMSIZE_KB_4096
195 default 0x800000 if UBOOT_ROMSIZE_KB_8192
196 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
197 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
200 bool "Platform requires Intel Management Engine"
202 Newer higher-end devices have an Intel Management Engine (ME)
203 which is a very large binary blob (typically 1.5MB) which is
204 required for the platform to work. This enforces a particular
205 SPI flash format. You will need to supply the me.bin file in
206 your board directory.
209 bool "Perform a simple RAM test after SDRAM initialisation"
211 If there is something wrong with SDRAM then the platform will
212 often crash within U-Boot or the kernel. This option enables a
213 very simple RAM test that quickly checks whether the SDRAM seems
214 to work correctly. It is not exhaustive but can save time by
215 detecting obvious failures.
217 config MARK_GRAPHICS_MEM_WRCOMB
218 bool "Mark graphics memory as write-combining."
221 The graphics performance may increase if the graphics
222 memory is set as write-combining cache type. This option
223 enables marking the graphics memory as write-combining.
227 config FRAMEBUFFER_SET_VESA_MODE
228 prompt "Set framebuffer graphics resolution"
231 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
234 prompt "framebuffer graphics resolution"
235 default FRAMEBUFFER_VESA_MODE_117
236 depends on FRAMEBUFFER_SET_VESA_MODE
238 This option sets the resolution used for the coreboot framebuffer (and
241 config FRAMEBUFFER_VESA_MODE_100
242 bool "640x400 256-color"
244 config FRAMEBUFFER_VESA_MODE_101
245 bool "640x480 256-color"
247 config FRAMEBUFFER_VESA_MODE_102
248 bool "800x600 16-color"
250 config FRAMEBUFFER_VESA_MODE_103
251 bool "800x600 256-color"
253 config FRAMEBUFFER_VESA_MODE_104
254 bool "1024x768 16-color"
256 config FRAMEBUFFER_VESA_MODE_105
257 bool "1024x7686 256-color"
259 config FRAMEBUFFER_VESA_MODE_106
260 bool "1280x1024 16-color"
262 config FRAMEBUFFER_VESA_MODE_107
263 bool "1280x1024 256-color"
265 config FRAMEBUFFER_VESA_MODE_108
268 config FRAMEBUFFER_VESA_MODE_109
271 config FRAMEBUFFER_VESA_MODE_10A
274 config FRAMEBUFFER_VESA_MODE_10B
277 config FRAMEBUFFER_VESA_MODE_10C
280 config FRAMEBUFFER_VESA_MODE_10D
281 bool "320x200 32k-color (1:5:5:5)"
283 config FRAMEBUFFER_VESA_MODE_10E
284 bool "320x200 64k-color (5:6:5)"
286 config FRAMEBUFFER_VESA_MODE_10F
287 bool "320x200 16.8M-color (8:8:8)"
289 config FRAMEBUFFER_VESA_MODE_110
290 bool "640x480 32k-color (1:5:5:5)"
292 config FRAMEBUFFER_VESA_MODE_111
293 bool "640x480 64k-color (5:6:5)"
295 config FRAMEBUFFER_VESA_MODE_112
296 bool "640x480 16.8M-color (8:8:8)"
298 config FRAMEBUFFER_VESA_MODE_113
299 bool "800x600 32k-color (1:5:5:5)"
301 config FRAMEBUFFER_VESA_MODE_114
302 bool "800x600 64k-color (5:6:5)"
304 config FRAMEBUFFER_VESA_MODE_115
305 bool "800x600 16.8M-color (8:8:8)"
307 config FRAMEBUFFER_VESA_MODE_116
308 bool "1024x768 32k-color (1:5:5:5)"
310 config FRAMEBUFFER_VESA_MODE_117
311 bool "1024x768 64k-color (5:6:5)"
313 config FRAMEBUFFER_VESA_MODE_118
314 bool "1024x768 16.8M-color (8:8:8)"
316 config FRAMEBUFFER_VESA_MODE_119
317 bool "1280x1024 32k-color (1:5:5:5)"
319 config FRAMEBUFFER_VESA_MODE_11A
320 bool "1280x1024 64k-color (5:6:5)"
322 config FRAMEBUFFER_VESA_MODE_11B
323 bool "1280x1024 16.8M-color (8:8:8)"
325 config FRAMEBUFFER_VESA_MODE_USER
326 bool "Manually select VESA mode"
330 # Map the config names to an integer (KB).
331 config FRAMEBUFFER_VESA_MODE
332 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
334 default 0x100 if FRAMEBUFFER_VESA_MODE_100
335 default 0x101 if FRAMEBUFFER_VESA_MODE_101
336 default 0x102 if FRAMEBUFFER_VESA_MODE_102
337 default 0x103 if FRAMEBUFFER_VESA_MODE_103
338 default 0x104 if FRAMEBUFFER_VESA_MODE_104
339 default 0x105 if FRAMEBUFFER_VESA_MODE_105
340 default 0x106 if FRAMEBUFFER_VESA_MODE_106
341 default 0x107 if FRAMEBUFFER_VESA_MODE_107
342 default 0x108 if FRAMEBUFFER_VESA_MODE_108
343 default 0x109 if FRAMEBUFFER_VESA_MODE_109
344 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
345 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
346 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
347 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
348 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
349 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
350 default 0x110 if FRAMEBUFFER_VESA_MODE_110
351 default 0x111 if FRAMEBUFFER_VESA_MODE_111
352 default 0x112 if FRAMEBUFFER_VESA_MODE_112
353 default 0x113 if FRAMEBUFFER_VESA_MODE_113
354 default 0x114 if FRAMEBUFFER_VESA_MODE_114
355 default 0x115 if FRAMEBUFFER_VESA_MODE_115
356 default 0x116 if FRAMEBUFFER_VESA_MODE_116
357 default 0x117 if FRAMEBUFFER_VESA_MODE_117
358 default 0x118 if FRAMEBUFFER_VESA_MODE_118
359 default 0x119 if FRAMEBUFFER_VESA_MODE_119
360 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
361 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
362 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
367 bool "Add an Firmware Support Package binary"
369 Select this option to add an Firmware Support Package binary to
370 the resulting U-Boot image. It is a binary blob which U-Boot uses
371 to set up SDRAM and other chipset specific initialization.
373 Note: Without this binary U-Boot will not be able to set up its
374 SDRAM so will not boot.
377 string "Firmware Support Package binary filename"
381 The filename of the file to use as Firmware Support Package binary
382 in the board directory.
385 hex "Firmware Support Package binary location"
389 FSP is not Position Independent Code (PIC) and the whole FSP has to
390 be rebased if it is placed at a location which is different from the
391 perferred base address specified during the FSP build. Use Intel's
392 Binary Configuration Tool (BCT) to do the rebase.
394 The default base address of 0xfffc0000 indicates that the binary must
395 be located at offset 0xc0000 from the beginning of a 1MB flash device.
397 config FSP_TEMP_RAM_ADDR
401 Stack top address which is used in FspInit after DRAM is ready and
404 source "arch/x86/cpu/baytrail/Kconfig"
406 source "arch/x86/cpu/coreboot/Kconfig"
408 source "arch/x86/cpu/ivybridge/Kconfig"
410 source "arch/x86/cpu/quark/Kconfig"
412 source "arch/x86/cpu/queensbay/Kconfig"
414 config TSC_CALIBRATION_BYPASS
415 bool "Bypass Time-Stamp Counter (TSC) calibration"
418 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
419 running frequency via Model-Specific Register (MSR) and Programmable
420 Interval Timer (PIT). If the calibration does not work on your board,
421 select this option and provide a hardcoded TSC running frequency with
422 CONFIG_TSC_FREQ_IN_MHZ below.
424 Normally this option should be turned on in a simulation environment
427 config TSC_FREQ_IN_MHZ
428 int "Time-Stamp Counter (TSC) running frequency in MHz"
429 depends on TSC_CALIBRATION_BYPASS
432 The running frequency in MHz of Time-Stamp Counter (TSC).
434 source "board/coreboot/coreboot/Kconfig"
436 source "board/google/chromebook_link/Kconfig"
438 source "board/intel/crownbay/Kconfig"
440 source "board/intel/minnowmax/Kconfig"
442 source "board/intel/galileo/Kconfig"
444 config PCIE_ECAM_BASE
448 This is the memory-mapped address of PCI configuration space, which
449 is only available through the Enhanced Configuration Access
450 Mechanism (ECAM) with PCI Express. It can be set up almost
451 anywhere. Before it is set up, it is possible to access PCI
452 configuration space through I/O access, but memory access is more
453 convenient. Using this, PCI can be scanned and configured. This
454 should be set to a region that does not conflict with memory
455 assigned to PCI devices - i.e. the memory and prefetch regions, as
456 passed to pci_set_region().