1 menu "x86 architecture"
8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
20 experimental and is missing a lot of features.
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28 to 64-bit just before starting the kernel. Only the bottom 4GB of
29 memory can be accessed through normal means, although
30 arch_phys_memset() can be used for basic access to other memory.
36 select SPL_SEPARATE_BSS
38 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
39 experimental and many features are missing. U-Boot SPL starts up,
40 runs through the 16-bit and 32-bit init, then switches to 64-bit
41 mode and jumps to U-Boot proper.
53 prompt "Mainboard vendor"
54 default VENDOR_EMULATION
56 config VENDOR_ADVANTECH
59 config VENDOR_CONGATEC
62 config VENDOR_COREBOOT
71 config VENDOR_EMULATION
82 # subarchitectures-specific options below
84 bool "Intel MID platform support"
88 Select to build a U-Boot capable of supporting Intel MID
89 (Mobile Internet Device) platform systems which do not have
90 the PCI legacy interfaces.
92 If you are building for a PC class system say N here.
94 Intel MID platforms are based on an Intel processor and
95 chipset which consume less power than most of the x86
98 # board-specific options below
99 source "board/advantech/Kconfig"
100 source "board/congatec/Kconfig"
101 source "board/coreboot/Kconfig"
102 source "board/dfi/Kconfig"
103 source "board/efi/Kconfig"
104 source "board/emulation/Kconfig"
105 source "board/google/Kconfig"
106 source "board/intel/Kconfig"
108 # platform-specific options below
109 source "arch/x86/cpu/baytrail/Kconfig"
110 source "arch/x86/cpu/braswell/Kconfig"
111 source "arch/x86/cpu/broadwell/Kconfig"
112 source "arch/x86/cpu/coreboot/Kconfig"
113 source "arch/x86/cpu/ivybridge/Kconfig"
114 source "arch/x86/cpu/efi/Kconfig"
115 source "arch/x86/cpu/qemu/Kconfig"
116 source "arch/x86/cpu/quark/Kconfig"
117 source "arch/x86/cpu/queensbay/Kconfig"
118 source "arch/x86/cpu/slimbootloader/Kconfig"
119 source "arch/x86/cpu/tangier/Kconfig"
121 # architecture-specific options below
126 config SYS_MALLOC_F_LEN
135 depends on X86_RESET_VECTOR
144 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
153 config X86_RESET_VECTOR
158 # The following options control where the 16-bit and 32-bit init lies
159 # If SPL is enabled then it normally holds this init code, and U-Boot proper
160 # is normally a 64-bit build.
162 # The 16-bit init refers to the reset vector and the small amount of code to
163 # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
164 # or missing altogether if U-Boot is started from EFI or coreboot.
166 # The 32-bit init refers to processor init, running binary blobs including
167 # FSP, setting up interrupts and anything else that needs to be done in
168 # 32-bit code. It is normally in the same place as 16-bit init if that is
169 # enabled (i.e. they are both in SPL, or both in U-Boot proper).
170 config X86_16BIT_INIT
172 depends on X86_RESET_VECTOR
173 default y if X86_RESET_VECTOR && !SPL
175 This is enabled when 16-bit init is in U-Boot proper
177 config SPL_X86_16BIT_INIT
179 depends on X86_RESET_VECTOR
180 default y if X86_RESET_VECTOR && SPL && !TPL
182 This is enabled when 16-bit init is in SPL
184 config TPL_X86_16BIT_INIT
186 depends on X86_RESET_VECTOR
187 default y if X86_RESET_VECTOR && TPL
189 This is enabled when 16-bit init is in TPL
191 config X86_32BIT_INIT
193 depends on X86_RESET_VECTOR
194 default y if X86_RESET_VECTOR && !SPL
196 This is enabled when 32-bit init is in U-Boot proper
198 config SPL_X86_32BIT_INIT
200 depends on X86_RESET_VECTOR
201 default y if X86_RESET_VECTOR && SPL
203 This is enabled when 32-bit init is in SPL
205 config RESET_SEG_START
207 depends on X86_RESET_VECTOR
212 depends on X86_RESET_VECTOR
215 config SYS_X86_START16
217 depends on X86_RESET_VECTOR
223 Enable inclusion of an Intel Firmware Interface Table (FIT) into the
224 image. This table is supposed to point to microcode and the like. So
225 far it is just a fixed table with the minimum set of headers, so that
226 it is actually present.
228 config X86_LOAD_FROM_32_BIT
229 bool "Boot from a 32-bit program"
231 Define this to boot U-Boot from a 32-bit program which sets
232 the GDT differently. This can be used to boot directly from
233 any stage of coreboot, for example, bypassing the normal
234 payload-loading feature.
236 config BOARD_ROMSIZE_KB_512
238 config BOARD_ROMSIZE_KB_1024
240 config BOARD_ROMSIZE_KB_2048
242 config BOARD_ROMSIZE_KB_4096
244 config BOARD_ROMSIZE_KB_8192
246 config BOARD_ROMSIZE_KB_16384
250 prompt "ROM chip size"
251 depends on X86_RESET_VECTOR
252 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
253 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
254 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
255 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
256 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
257 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
259 Select the size of the ROM chip you intend to flash U-Boot on.
261 The build system will take care of creating a u-boot.rom file
262 of the matching size.
264 config UBOOT_ROMSIZE_KB_512
267 Choose this option if you have a 512 KB ROM chip.
269 config UBOOT_ROMSIZE_KB_1024
270 bool "1024 KB (1 MB)"
272 Choose this option if you have a 1024 KB (1 MB) ROM chip.
274 config UBOOT_ROMSIZE_KB_2048
275 bool "2048 KB (2 MB)"
277 Choose this option if you have a 2048 KB (2 MB) ROM chip.
279 config UBOOT_ROMSIZE_KB_4096
280 bool "4096 KB (4 MB)"
282 Choose this option if you have a 4096 KB (4 MB) ROM chip.
284 config UBOOT_ROMSIZE_KB_8192
285 bool "8192 KB (8 MB)"
287 Choose this option if you have a 8192 KB (8 MB) ROM chip.
289 config UBOOT_ROMSIZE_KB_16384
290 bool "16384 KB (16 MB)"
292 Choose this option if you have a 16384 KB (16 MB) ROM chip.
296 # Map the config names to an integer (KB).
297 config UBOOT_ROMSIZE_KB
299 default 512 if UBOOT_ROMSIZE_KB_512
300 default 1024 if UBOOT_ROMSIZE_KB_1024
301 default 2048 if UBOOT_ROMSIZE_KB_2048
302 default 4096 if UBOOT_ROMSIZE_KB_4096
303 default 8192 if UBOOT_ROMSIZE_KB_8192
304 default 16384 if UBOOT_ROMSIZE_KB_16384
306 # Map the config names to a hex value (bytes).
309 default 0x80000 if UBOOT_ROMSIZE_KB_512
310 default 0x100000 if UBOOT_ROMSIZE_KB_1024
311 default 0x200000 if UBOOT_ROMSIZE_KB_2048
312 default 0x400000 if UBOOT_ROMSIZE_KB_4096
313 default 0x800000 if UBOOT_ROMSIZE_KB_8192
314 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
315 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
318 bool "Platform requires Intel Management Engine"
320 Newer higher-end devices have an Intel Management Engine (ME)
321 which is a very large binary blob (typically 1.5MB) which is
322 required for the platform to work. This enforces a particular
323 SPI flash format. You will need to supply the me.bin file in
324 your board directory.
327 bool "Perform a simple RAM test after SDRAM initialisation"
329 If there is something wrong with SDRAM then the platform will
330 often crash within U-Boot or the kernel. This option enables a
331 very simple RAM test that quickly checks whether the SDRAM seems
332 to work correctly. It is not exhaustive but can save time by
333 detecting obvious failures.
335 config FLASH_DESCRIPTOR_FILE
336 string "Flash descriptor binary filename"
337 depends on HAVE_INTEL_ME || FSP_VERSION2
338 default "descriptor.bin"
340 The filename of the file to use as flash descriptor in the
344 string "Intel Management Engine binary filename"
345 depends on HAVE_INTEL_ME
348 The filename of the file to use as Intel Management Engine in the
352 bool "Use HOB (Hand-Off Block)"
354 Select this option to access HOB (Hand-Off Block) data structures
355 and parse HOBs. This HOB infra structure can be reused with
356 different solutions across different platforms.
359 bool "Add an Firmware Support Package binary"
363 Select this option to add an Firmware Support Package binary to
364 the resulting U-Boot image. It is a binary blob which U-Boot uses
365 to set up SDRAM and other chipset specific initialization.
367 Note: Without this binary U-Boot will not be able to set up its
368 SDRAM so will not boot.
371 bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
372 default y if !HAVE_FSP
374 Select this option if your board uses CAR init code, typically in a
375 car.S file, to get some initial memory for code execution. This is
376 common with Intel CPUs which don't use FSP.
383 Selects the FSP version to use. Intel has published several versions
384 of the FSP External Architecture Specification and this allows
385 selection of the version number used by a particular SoC.
388 bool "FSP version 1.x"
390 This covers versions 1.0 and 1.1a. See here for details:
391 https://github.com/IntelFsp/fsp/wiki
394 bool "FSP version 2.x"
396 This covers versions 2.0 and 2.1. See here for details:
397 https://github.com/IntelFsp/fsp/wiki
402 string "Firmware Support Package binary filename"
403 depends on FSP_VERSION1
406 The filename of the file to use as Firmware Support Package binary
407 in the board directory.
410 hex "Firmware Support Package binary location"
411 depends on FSP_VERSION1
414 FSP is not Position Independent Code (PIC) and the whole FSP has to
415 be rebased if it is placed at a location which is different from the
416 perferred base address specified during the FSP build. Use Intel's
417 Binary Configuration Tool (BCT) to do the rebase.
419 The default base address of 0xfffc0000 indicates that the binary must
420 be located at offset 0xc0000 from the beginning of a 1MB flash device.
425 string "Firmware Support Package binary filename (Temp RAM)"
428 The filename of the file to use for the temporary-RAM init phase from
429 the Firmware Support Package binary. Put this in the board directory.
430 It is used to set up an initial area of RAM which can be used for the
431 stack and other purposes, while bringing up the main system DRAM.
434 hex "Firmware Support Package binary location (Temp RAM)"
437 FSP is not Position-Independent Code (PIC) and FSP components have to
438 be rebased if placed at a location which is different from the
439 perferred base address specified during the FSP build. Use Intel's
440 Binary Configuration Tool (BCT) to do the rebase.
443 string "Firmware Support Package binary filename (Memory Init)"
446 The filename of the file to use for the RAM init phase from the
447 Firmware Support Package binary. Put this in the board directory.
448 It is used to set up the main system DRAM and runs in SPL, once
449 temporary RAM (CAR) is working.
452 string "Firmware Support Package binary filename (Silicon Init)"
455 The filename of the file to use for the Silicon init phase from the
456 Firmware Support Package binary. Put this in the board directory.
457 It is used to set up the silicon to work correctly and must be
458 executed after DRAM is running.
460 config IFWI_INPUT_FILE
461 string "Filename containing FIT (Firmware Interface Table) with IFWI"
462 default "fitimage.bin"
464 The IFWI is obtained by running a tool on this file to extract the
465 IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
466 microcode and other internal items.
470 config FSP_TEMP_RAM_ADDR
472 depends on FSP_VERSION1
475 Stack top address which is used in fsp_init() after DRAM is ready and
478 config FSP_SYS_MALLOC_F_LEN
480 depends on FSP_VERSION1
483 Additional size of malloc() pool before relocation.
487 depends on FSP_VERSION1
490 Most FSPs use UPD data region for some FSP customization. But there
491 are still some FSPs that might not even have UPD. For such FSPs,
492 override this to n in their platform Kconfig files.
494 config FSP_BROKEN_HOB
496 depends on FSP_VERSION1
498 Indicate some buggy FSPs that does not report memory used by FSP
499 itself as reserved in the resource descriptor HOB. Select this to
500 tell U-Boot to do some additional work to ensure U-Boot relocation
501 do not overwrite the important boot service data which is used by
502 FSP, otherwise the subsequent call to fsp_notify() will fail.
504 config ENABLE_MRC_CACHE
505 bool "Enable MRC cache"
506 depends on !EFI && !SYS_COREBOOT
508 Enable this feature to cause MRC data to be cached in NV storage
509 to be used for speeding up boot time on future reboots and/or
512 For platforms that use Intel FSP for the memory initialization,
513 please check FSP output HOB via U-Boot command 'fsp hob' to see
514 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
515 If such GUID does not exist, MRC cache is not available on such
516 platform (eg: Intel Queensbay), which means selecting this option
517 here does not make any difference.
520 bool "Add a System Agent binary"
523 Select this option to add a System Agent binary to
524 the resulting U-Boot image. MRC stands for Memory Reference Code.
525 It is a binary blob which U-Boot uses to set up SDRAM.
527 Note: Without this binary U-Boot will not be able to set up its
528 SDRAM so will not boot.
535 Enable caching for the memory reference code binary. This uses an
536 MTRR (memory type range register) to turn on caching for the section
537 of SPI flash that contains the memory reference code. This makes
538 SDRAM init run faster.
540 config CACHE_MRC_SIZE_KB
545 Sets the size of the cached area for the memory reference code.
546 This ends at the end of SPI flash (address 0xffffffff) and is
547 measured in KB. Typically this is set to 512, providing for 0.5MB
550 config DCACHE_RAM_BASE
554 Sets the base of the data cache area in memory space. This is the
555 start address of the cache-as-RAM (CAR) area and the address varies
556 depending on the CPU. Once CAR is set up, read/write memory becomes
557 available at this address and can be used temporarily until SDRAM
560 config DCACHE_RAM_SIZE
565 Sets the total size of the data cache area in memory space. This
566 sets the size of the cache-as-RAM (CAR) area. Note that much of the
567 CAR space is required by the MRC. The CAR space available to U-Boot
568 is normally at the start and typically extends to 1/4 or 1/2 of the
571 config DCACHE_RAM_MRC_VAR_SIZE
575 This is the amount of CAR (Cache as RAM) reserved for use by the
576 memory reference code. This depends on the implementation of the
577 memory reference code and must be set correctly or the board will
581 bool "Add a Reference Code binary"
583 Select this option to add a Reference Code binary to the resulting
584 U-Boot image. This is an Intel binary blob that handles system
585 initialisation, in this case the PCH and System Agent.
587 Note: Without this binary (on platforms that need it such as
588 broadwell) U-Boot will be missing some critical setup steps.
589 Various peripherals may fail to work.
591 config HAVE_MICROCODE
593 default y if !FSP_VERSION2
596 bool "Enable Symmetric Multiprocessing"
599 Enable use of more than one CPU in U-Boot and the Operating System
600 when loaded. Each CPU will be started up and information can be
601 obtained using the 'cpu' command. If this option is disabled, then
602 only one CPU will be enabled regardless of the number of CPUs
606 int "Maximum number of CPUs permitted"
610 When using multi-CPU chips it is possible for U-Boot to start up
611 more than one CPU. The stack memory used by all of these CPUs is
612 pre-allocated so at present U-Boot wants to know the maximum
613 number of CPUs that may be present. Set this to at least as high
614 as the number of CPUs in your system (it uses about 4KB of RAM for
622 Each additional CPU started by U-Boot requires its own stack. This
623 option sets the stack size used by each CPU and directly affects
624 the memory used by this initialisation process. Typically 4KB is
627 config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
630 This option indicates that the turbo mode setting is not package
631 scoped. i.e. turbo_enable() needs to be called on not just the
632 bootstrap processor (BSP).
635 bool "Add a VGA BIOS image"
637 Select this option if you have a VGA BIOS image that you would
638 like to add to your ROM.
641 string "VGA BIOS image filename"
642 depends on HAVE_VGA_BIOS
645 The filename of the VGA BIOS image in the board directory.
648 hex "VGA BIOS image location"
649 depends on HAVE_VGA_BIOS
652 The location of VGA BIOS image in the SPI flash. For example, base
653 address of 0xfff90000 indicates that the image will be put at offset
654 0x90000 from the beginning of a 1MB flash device.
657 bool "Add a Video BIOS Table (VBT) image"
660 Select this option if you have a Video BIOS Table (VBT) image that
661 you would like to add to your ROM. This is normally required if you
662 are using an Intel FSP firmware that is complaint with spec 1.1 or
663 later to initialize the integrated graphics device (IGD).
665 Video BIOS Table, or VBT, provides platform and board specific
666 configuration information to the driver that is not discoverable
667 or available through other means. By other means the most used
668 method here is to read EDID table from the attached monitor, over
669 Display Data Channel (DDC) using two pin I2C serial interface. VBT
670 configuration is related to display hardware and is available via
671 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
674 string "Video BIOS Table (VBT) image filename"
678 The filename of the file to use as Video BIOS Table (VBT) image
679 in the board directory.
682 hex "Video BIOS Table (VBT) image location"
686 The location of Video BIOS Table (VBT) image in the SPI flash. For
687 example, base address of 0xfff90000 indicates that the image will
688 be put at offset 0x90000 from the beginning of a 1MB flash device.
691 bool "Enable FSP framebuffer driver support"
692 depends on HAVE_VBT && DM_VIDEO
694 Turn on this option to enable a framebuffer driver when U-Boot is
695 using Video BIOS Table (VBT) image for FSP firmware to initialize
696 the integrated graphics device.
698 config ROM_TABLE_ADDR
702 All x86 tables happen to like the address range from 0x0f0000
703 to 0x100000. We use 0xf0000 as the starting address to store
704 those tables, including PIRQ routing table, Multi-Processor
705 table and ACPI table.
707 config ROM_TABLE_SIZE
712 depends on !EFI && !SYS_COREBOOT
714 config GENERATE_PIRQ_TABLE
715 bool "Generate a PIRQ table"
718 Generate a PIRQ routing table for this board. The PIRQ routing table
719 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
720 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
721 It specifies the interrupt router information as well how all the PCI
722 devices' interrupt pins are wired to PIRQs.
724 config GENERATE_SFI_TABLE
725 bool "Generate a SFI (Simple Firmware Interface) table"
727 The Simple Firmware Interface (SFI) provides a lightweight method
728 for platform firmware to pass information to the operating system
729 via static tables in memory. Kernel SFI support is required to
730 boot on SFI-only platforms. If you have ACPI tables then these are
733 U-Boot writes this table in write_sfi_table() just before booting
736 For more information, see http://simplefirmware.org
738 config GENERATE_MP_TABLE
739 bool "Generate an MP (Multi-Processor) table"
742 Generate an MP (Multi-Processor) table for this board. The MP table
743 provides a way for the operating system to support for symmetric
744 multiprocessing as well as symmetric I/O interrupt handling with
745 the local APIC and I/O APIC.
747 config GENERATE_ACPI_TABLE
748 bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
752 The Advanced Configuration and Power Interface (ACPI) specification
753 provides an open standard for device configuration and management
754 by the operating system. It defines platform-independent interfaces
755 for configuration and power management monitoring.
759 config HAVE_ACPI_RESUME
760 bool "Enable ACPI S3 resume"
761 select ENABLE_MRC_CACHE
763 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
764 state where all system context is lost except system memory. U-Boot
765 is responsible for restoring the machine state as it was before sleep.
766 It needs restore the memory controller, without overwriting memory
767 which is not marked as reserved. For the peripherals which lose their
768 registers, U-Boot needs to write the original value. When everything
769 is done, U-Boot needs to find out the wakeup vector provided by OSes
772 config S3_VGA_ROM_RUN
773 bool "Re-run VGA option ROMs on S3 resume"
774 depends on HAVE_ACPI_RESUME
776 Execute VGA option ROMs in U-Boot when resuming from S3. Normally
777 this is needed when graphics console is being used in the kernel.
779 Turning it off can reduce some resume time, but be aware that your
780 graphics console won't work without VGA options ROMs. Set it to N
781 if your kernel is only on a serial console.
785 depends on HAVE_ACPI_RESUME
788 Estimated U-Boot's runtime stack size that needs to be reserved
789 during an ACPI S3 resume.
791 config MAX_PIRQ_LINKS
795 This variable specifies the number of PIRQ interrupt links which are
796 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
797 Some newer chipsets offer more than four links, commonly up to PIRQH.
799 config IRQ_SLOT_COUNT
803 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
804 which in turns forms a table of exact 4KiB. The default value 128
805 should be enough for most boards. If this does not fit your board,
806 change it according to your needs.
808 config PCIE_ECAM_BASE
812 This is the memory-mapped address of PCI configuration space, which
813 is only available through the Enhanced Configuration Access
814 Mechanism (ECAM) with PCI Express. It can be set up almost
815 anywhere. Before it is set up, it is possible to access PCI
816 configuration space through I/O access, but memory access is more
817 convenient. Using this, PCI can be scanned and configured. This
818 should be set to a region that does not conflict with memory
819 assigned to PCI devices - i.e. the memory and prefetch regions, as
820 passed to pci_set_region().
822 config PCIE_ECAM_SIZE
826 This is the size of memory-mapped address of PCI configuration space,
827 which is only available through the Enhanced Configuration Access
828 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
829 so a default 0x10000000 size covers all of the 256 buses which is the
830 maximum number of PCI buses as defined by the PCI specification.
833 bool "Enable Intel 8259 compatible interrupt controller"
836 Intel 8259 ISA compatible chipset incorporates two 8259 (master and
837 slave) interrupt controllers. Include this to have U-Boot set up
838 the interrupt correctly.
841 bool "Enable Intel Advanced Programmable Interrupt Controller"
844 The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
845 for catching interrupts and distributing them to one or more CPU
846 cores. In most cases there are some LAPICs (local) for each core and
847 one I/O APIC. This conjunction is found on most modern x86 systems.
852 Intel ICH6 compatible chipset pinctrl driver. It needs to work
853 together with the ICH6 compatible gpio driver.
859 Intel 8254 timer contains three counters which have fixed uses.
860 Include this to have U-Boot set up the timer correctly.
863 bool "Support booting SeaBIOS"
865 SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
866 It can run in an emulator or natively on X86 hardware with the use
867 of coreboot/U-Boot. By turning on this option, U-Boot prepares
868 all the configuration tables that are necessary to boot SeaBIOS.
870 Check http://www.seabios.org/SeaBIOS for details.
872 config HIGH_TABLE_SIZE
873 hex "Size of configuration tables which reside in high memory"
877 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
878 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
879 puts a copy of configuration tables in high memory region which
880 is reserved on the stack before relocation. The region size is
881 determined by this option.
883 Increse it if the default size does not fit the board's needs.
884 This is most likely due to a large ACPI DSDT table is used.
886 config INTEL_CAR_CQOS
887 bool "Support Intel Cache Quality of Service"
889 Cache Quality of Service allows more fine-grained control of cache
890 usage. As result, it is possible to set up a portion of L2 cache for
891 CAR and use the remainder for actual caching.
894 # Each bit in QOS mask controls this many bytes. This is calculated as:
895 # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
897 config CACHE_QOS_SIZE_PER_BIT
899 depends on INTEL_CAR_CQOS
900 default 0x20000 # 128 KB
902 config X86_OFFSET_U_BOOT
903 hex "Offset of U-Boot in ROM image"
904 depends on HAVE_SYS_TEXT_BASE
905 default SYS_TEXT_BASE
907 config X86_OFFSET_SPL
908 hex "Offset of SPL in ROM image"
909 depends on SPL && X86
910 default SPL_TEXT_BASE