arch/sh/kernel/cpu/sh4a/setup-sh7343.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7343 Setup
   4  *
   5  *  Copyright (C) 2006  Paul Mundt
   6  */
   7 #include <linux/platform_device.h>
   8 #include <linux/init.h>
   9 #include <linux/serial.h>
  10 #include <linux/serial_sci.h>
  11 #include <linux/uio_driver.h>
  12 #include <linux/sh_timer.h>
  13 #include <linux/sh_intc.h>
  14 #include <asm/clock.h>
  15
  16 /* Serial */
  17 static struct plat_sci_port scif0_platform_data = {
  18         .scscr          = SCSCR_CKE1,
  19         .type           = PORT_SCIF,
  20 };
  21
  22 static struct resource scif0_resources[] = {
  23         DEFINE_RES_MEM(0xffe00000, 0x100),
  24         DEFINE_RES_IRQ(evt2irq(0xc00)),
  25 };
  26
  27 static struct platform_device scif0_device = {
  28         .name           = "sh-sci",
  29         .id             = 0,
  30         .resource       = scif0_resources,
  31         .num_resources  = ARRAY_SIZE(scif0_resources),
  32         .dev            = {
  33                 .platform_data  = &scif0_platform_data,
  34         },
  35 };
  36
  37 static struct plat_sci_port scif1_platform_data = {
  38         .scscr          = SCSCR_CKE1,
  39         .type           = PORT_SCIF,
  40 };
  41
  42 static struct resource scif1_resources[] = {
  43         DEFINE_RES_MEM(0xffe10000, 0x100),
  44         DEFINE_RES_IRQ(evt2irq(0xc20)),
  45 };
  46
  47 static struct platform_device scif1_device = {
  48         .name           = "sh-sci",
  49         .id             = 1,
  50         .resource       = scif1_resources,
  51         .num_resources  = ARRAY_SIZE(scif1_resources),
  52         .dev            = {
  53                 .platform_data  = &scif1_platform_data,
  54         },
  55 };
  56
  57 static struct plat_sci_port scif2_platform_data = {
  58         .scscr          = SCSCR_CKE1,
  59         .type           = PORT_SCIF,
  60 };
  61
  62 static struct resource scif2_resources[] = {
  63         DEFINE_RES_MEM(0xffe20000, 0x100),
  64         DEFINE_RES_IRQ(evt2irq(0xc40)),
  65 };
  66
  67 static struct platform_device scif2_device = {
  68         .name           = "sh-sci",
  69         .id             = 2,
  70         .resource       = scif2_resources,
  71         .num_resources  = ARRAY_SIZE(scif2_resources),
  72         .dev            = {
  73                 .platform_data  = &scif2_platform_data,
  74         },
  75 };
  76
  77 static struct plat_sci_port scif3_platform_data = {
  78         .scscr          = SCSCR_CKE1,
  79         .type           = PORT_SCIF,
  80 };
  81
  82 static struct resource scif3_resources[] = {
  83         DEFINE_RES_MEM(0xffe30000, 0x100),
  84         DEFINE_RES_IRQ(evt2irq(0xc60)),
  85 };
  86
  87 static struct platform_device scif3_device = {
  88         .name           = "sh-sci",
  89         .id             = 3,
  90         .resource       = scif3_resources,
  91         .num_resources  = ARRAY_SIZE(scif3_resources),
  92         .dev            = {
  93                 .platform_data  = &scif3_platform_data,
  94         },
  95 };
  96
  97 static struct resource iic0_resources[] = {
  98         [0] = {
  99                 .name   = "IIC0",
 100                 .start  = 0x04470000,
 101                 .end    = 0x04470017,
 102                 .flags  = IORESOURCE_MEM,
 103         },
 104         [1] = {
 105                 .start  = evt2irq(0xe00),
 106                 .end    = evt2irq(0xe60),
 107                 .flags  = IORESOURCE_IRQ,
 108        },
 109 };
 110
 111 static struct platform_device iic0_device = {
 112         .name           = "i2c-sh_mobile",
 113         .id             = 0, /* "i2c0" clock */
 114         .num_resources  = ARRAY_SIZE(iic0_resources),
 115         .resource       = iic0_resources,
 116 };
 117
 118 static struct resource iic1_resources[] = {
 119         [0] = {
 120                 .name   = "IIC1",
 121                 .start  = 0x04750000,
 122                 .end    = 0x04750017,
 123                 .flags  = IORESOURCE_MEM,
 124         },
 125         [1] = {
 126                 .start  = evt2irq(0x780),
 127                 .end    = evt2irq(0x7e0),
 128                 .flags  = IORESOURCE_IRQ,
 129        },
 130 };
 131
 132 static struct platform_device iic1_device = {
 133         .name           = "i2c-sh_mobile",
 134         .id             = 1, /* "i2c1" clock */
 135         .num_resources  = ARRAY_SIZE(iic1_resources),
 136         .resource       = iic1_resources,
 137 };
 138
 139 static struct uio_info vpu_platform_data = {
 140         .name = "VPU4",
 141         .version = "0",
 142         .irq = evt2irq(0x980),
 143 };
 144
 145 static struct resource vpu_resources[] = {
 146         [0] = {
 147                 .name   = "VPU",
 148                 .start  = 0xfe900000,
 149                 .end    = 0xfe9022eb,
 150                 .flags  = IORESOURCE_MEM,
 151         },
 152         [1] = {
 153                 /* place holder for contiguous memory */
 154         },
 155 };
 156
 157 static struct platform_device vpu_device = {
 158         .name           = "uio_pdrv_genirq",
 159         .id             = 0,
 160         .dev = {
 161                 .platform_data  = &vpu_platform_data,
 162         },
 163         .resource       = vpu_resources,
 164         .num_resources  = ARRAY_SIZE(vpu_resources),
 165 };
 166
 167 static struct uio_info veu_platform_data = {
 168         .name = "VEU",
 169         .version = "0",
 170         .irq = evt2irq(0x8c0),
 171 };
 172
 173 static struct resource veu_resources[] = {
 174         [0] = {
 175                 .name   = "VEU",
 176                 .start  = 0xfe920000,
 177                 .end    = 0xfe9200b7,
 178                 .flags  = IORESOURCE_MEM,
 179         },
 180         [1] = {
 181                 /* place holder for contiguous memory */
 182         },
 183 };
 184
 185 static struct platform_device veu_device = {
 186         .name           = "uio_pdrv_genirq",
 187         .id             = 1,
 188         .dev = {
 189                 .platform_data  = &veu_platform_data,
 190         },
 191         .resource       = veu_resources,
 192         .num_resources  = ARRAY_SIZE(veu_resources),
 193 };
 194
 195 static struct uio_info jpu_platform_data = {
 196         .name = "JPU",
 197         .version = "0",
 198         .irq = evt2irq(0x560),
 199 };
 200
 201 static struct resource jpu_resources[] = {
 202         [0] = {
 203                 .name   = "JPU",
 204                 .start  = 0xfea00000,
 205                 .end    = 0xfea102d3,
 206                 .flags  = IORESOURCE_MEM,
 207         },
 208         [1] = {
 209                 /* place holder for contiguous memory */
 210         },
 211 };
 212
 213 static struct platform_device jpu_device = {
 214         .name           = "uio_pdrv_genirq",
 215         .id             = 2,
 216         .dev = {
 217                 .platform_data  = &jpu_platform_data,
 218         },
 219         .resource       = jpu_resources,
 220         .num_resources  = ARRAY_SIZE(jpu_resources),
 221 };
 222
 223 static struct sh_timer_config cmt_platform_data = {
 224         .channels_mask = 0x20,
 225 };
 226
 227 static struct resource cmt_resources[] = {
 228         DEFINE_RES_MEM(0x044a0000, 0x70),
 229         DEFINE_RES_IRQ(evt2irq(0xf00)),
 230 };
 231
 232 static struct platform_device cmt_device = {
 233         .name           = "sh-cmt-32",
 234         .id             = 0,
 235         .dev = {
 236                 .platform_data  = &cmt_platform_data,
 237         },
 238         .resource       = cmt_resources,
 239         .num_resources  = ARRAY_SIZE(cmt_resources),
 240 };
 241
 242 static struct sh_timer_config tmu0_platform_data = {
 243         .channels_mask = 7,
 244 };
 245
 246 static struct resource tmu0_resources[] = {
 247         DEFINE_RES_MEM(0xffd80000, 0x2c),
 248         DEFINE_RES_IRQ(evt2irq(0x400)),
 249         DEFINE_RES_IRQ(evt2irq(0x420)),
 250         DEFINE_RES_IRQ(evt2irq(0x440)),
 251 };
 252
 253 static struct platform_device tmu0_device = {
 254         .name           = "sh-tmu",
 255         .id             = 0,
 256         .dev = {
 257                 .platform_data  = &tmu0_platform_data,
 258         },
 259         .resource       = tmu0_resources,
 260         .num_resources  = ARRAY_SIZE(tmu0_resources),
 261 };
 262
 263 static struct platform_device *sh7343_devices[] __initdata = {
 264         &scif0_device,
 265         &scif1_device,
 266         &scif2_device,
 267         &scif3_device,
 268         &cmt_device,
 269         &tmu0_device,
 270         &iic0_device,
 271         &iic1_device,
 272         &vpu_device,
 273         &veu_device,
 274         &jpu_device,
 275 };
 276
 277 static int __init sh7343_devices_setup(void)
 278 {
 279         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 280         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 281         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 282
 283         return platform_add_devices(sh7343_devices,
 284                                     ARRAY_SIZE(sh7343_devices));
 285 }
 286 arch_initcall(sh7343_devices_setup);
 287
 288 static struct platform_device *sh7343_early_devices[] __initdata = {
 289         &scif0_device,
 290         &scif1_device,
 291         &scif2_device,
 292         &scif3_device,
 293         &cmt_device,
 294         &tmu0_device,
 295 };
 296
 297 void __init plat_early_device_setup(void)
 298 {
 299         early_platform_add_devices(sh7343_early_devices,
 300                                    ARRAY_SIZE(sh7343_early_devices));
 301 }
 302
 303 enum {
 304         UNUSED = 0,
 305         ENABLED,
 306         DISABLED,
 307
 308         /* interrupt sources */
 309         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 310         DMAC0, DMAC1, DMAC2, DMAC3,
 311         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 312         MFI, VPU, TPU, Z3D4, USBI0, USBI1,
 313         MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
 314         DMAC4, DMAC5, DMAC_DADERR,
 315         KEYSC,
 316         SCIF, SCIF1, SCIF2, SCIF3,
 317         SIOF0, SIOF1, SIO,
 318         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 319         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
 320         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
 321         SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
 322         IRDA, SDHI, CMT, TSIF, SIU,
 323         TMU0, TMU1, TMU2,
 324         JPU, LCDC,
 325
 326         /* interrupt groups */
 327
 328         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
 329 };
 330
 331 static struct intc_vect vectors[] __initdata = {
 332         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 333         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 334         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 335         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 336         INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
 337         INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
 338         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 339         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 340         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 341         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 342         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
 343         INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
 344         INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
 345         INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
 346         INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
 347         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 348         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 349         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
 350         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
 351         INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
 352         INTC_VECT(SIO, 0xd00),
 353         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 354         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 355         INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
 356         INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
 357         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 358         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 359         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 360         INTC_VECT(SIU, 0xf80),
 361         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 362         INTC_VECT(TMU2, 0x440),
 363         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 364 };
 365
 366 static struct intc_group groups[] __initdata = {
 367         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 368         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 369         INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
 370         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 371         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 372                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 373         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
 374         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
 375         INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
 376         INTC_GROUP(USB, USBI0, USBI1),
 377 };
 378
 379 static struct intc_mask_reg mask_registers[] __initdata = {
 380         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 381           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 382         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 383           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 384         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 385           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 386         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 387           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 388         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 389           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
 390         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 391           { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
 392         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 393           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
 394             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 395         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 396           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
 397         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 398           { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
 399         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 400           { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
 401         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 402           { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
 403         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 404           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 405 };
 406
 407 static struct intc_prio_reg prio_registers[] __initdata = {
 408         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 409         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 410         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 411         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 412         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
 413         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
 414         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
 415         { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
 416         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 417         { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
 418         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 419           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 420 };
 421
 422 static struct intc_sense_reg sense_registers[] __initdata = {
 423         { 0xa414001c, 16, 2, /* ICR1 */
 424           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 425 };
 426
 427 static struct intc_mask_reg ack_registers[] __initdata = {
 428         { 0xa4140024, 0, 8, /* INTREQ00 */
 429           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 430 };
 431
 432 static struct intc_desc intc_desc __initdata = {
 433         .name = "sh7343",
 434         .force_enable = ENABLED,
 435         .force_disable = DISABLED,
 436         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 437                            prio_registers, sense_registers, ack_registers),
 438 };
 439
 440 void __init plat_irq_setup(void)
 441 {
 442         register_intc_controller(&intc_desc);
 443 }