arch/sh/kernel/cpu/sh3/probe.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/sh/kernel/cpu/sh3/probe.c
   4  *
   5  * CPU Subtype Probing for SH-3.
   6  *
   7  * Copyright (C) 1999, 2000  Niibe Yutaka
   8  * Copyright (C) 2002  Paul Mundt
   9  */
  10
  11 #include <linux/init.h>
  12 #include <asm/processor.h>
  13 #include <asm/cache.h>
  14 #include <asm/io.h>
  15
  16 void cpu_probe(void)
  17 {
  18         unsigned long addr0, addr1, data0, data1, data2, data3;
  19
  20         jump_to_uncached();
  21         /*
  22          * Check if the entry shadows or not.
  23          * When shadowed, it's 128-entry system.
  24          * Otherwise, it's 256-entry system.
  25          */
  26         addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
  27         addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
  28
  29         /* First, write back & invalidate */
  30         data0  = __raw_readl(addr0);
  31         __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
  32         data1  = __raw_readl(addr1);
  33         __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
  34
  35         /* Next, check if there's shadow or not */
  36         data0 = __raw_readl(addr0);
  37         data0 ^= SH_CACHE_VALID;
  38         __raw_writel(data0, addr0);
  39         data1 = __raw_readl(addr1);
  40         data2 = data1 ^ SH_CACHE_VALID;
  41         __raw_writel(data2, addr1);
  42         data3 = __raw_readl(addr0);
  43
  44         /* Lastly, invaliate them. */
  45         __raw_writel(data0&~SH_CACHE_VALID, addr0);
  46         __raw_writel(data2&~SH_CACHE_VALID, addr1);
  47
  48         back_to_cached();
  49
  50         boot_cpu_data.dcache.ways               = 4;
  51         boot_cpu_data.dcache.entry_shift        = 4;
  52         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  53         boot_cpu_data.dcache.flags              = 0;
  54
  55         /*
  56          * 7709A/7729 has 16K cache (256-entry), while 7702 has only
  57          * 2K(direct) 7702 is not supported (yet)
  58          */
  59         if (data0 == data1 && data2 == data3) { /* Shadow */
  60                 boot_cpu_data.dcache.way_incr   = (1 << 11);
  61                 boot_cpu_data.dcache.entry_mask = 0x7f0;
  62                 boot_cpu_data.dcache.sets       = 128;
  63                 boot_cpu_data.type = CPU_SH7708;
  64
  65                 boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
  66         } else {                                /* 7709A or 7729  */
  67                 boot_cpu_data.dcache.way_incr   = (1 << 12);
  68                 boot_cpu_data.dcache.entry_mask = 0xff0;
  69                 boot_cpu_data.dcache.sets       = 256;
  70                 boot_cpu_data.type = CPU_SH7729;
  71
  72 #if defined(CONFIG_CPU_SUBTYPE_SH7706)
  73                 boot_cpu_data.type = CPU_SH7706;
  74 #endif
  75 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
  76                 boot_cpu_data.type = CPU_SH7710;
  77 #endif
  78 #if defined(CONFIG_CPU_SUBTYPE_SH7712)
  79                 boot_cpu_data.type = CPU_SH7712;
  80 #endif
  81 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
  82                 boot_cpu_data.type = CPU_SH7720;
  83 #endif
  84 #if defined(CONFIG_CPU_SUBTYPE_SH7721)
  85                 boot_cpu_data.type = CPU_SH7721;
  86 #endif
  87 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
  88                 boot_cpu_data.type = CPU_SH7705;
  89
  90 #if defined(CONFIG_SH7705_CACHE_32KB)
  91                 boot_cpu_data.dcache.way_incr   = (1 << 13);
  92                 boot_cpu_data.dcache.entry_mask = 0x1ff0;
  93                 boot_cpu_data.dcache.sets       = 512;
  94                 __raw_writel(CCR_CACHE_32KB, CCR3_REG);
  95 #else
  96                 __raw_writel(CCR_CACHE_16KB, CCR3_REG);
  97 #endif
  98 #endif
  99         }
 100
 101         /*
 102          * SH-3 doesn't have separate caches
 103          */
 104         boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
 105         boot_cpu_data.icache = boot_cpu_data.dcache;
 106
 107         boot_cpu_data.family = CPU_FAMILY_SH3;
 108 }