arch/sh/include/cpu-sh4/cpu/dma-register.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * SH4 CPU-specific DMA definitions, used by both DMA drivers
   4  *
   5  * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  */
   7 #ifndef CPU_DMA_REGISTER_H
   8 #define CPU_DMA_REGISTER_H
   9
  10 /* SH7751/7760/7780 DMA IRQ sources */
  11
  12 #ifdef CONFIG_CPU_SH4A
  13
  14 #define DMAOR_INIT      DMAOR_DME
  15
  16 #if defined(CONFIG_CPU_SUBTYPE_SH7343)
  17 #define CHCR_TS_LOW_MASK        0x00000018
  18 #define CHCR_TS_LOW_SHIFT       3
  19 #define CHCR_TS_HIGH_MASK       0
  20 #define CHCR_TS_HIGH_SHIFT      0
  21 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
  22         defined(CONFIG_CPU_SUBTYPE_SH7723) || \
  23         defined(CONFIG_CPU_SUBTYPE_SH7724) || \
  24         defined(CONFIG_CPU_SUBTYPE_SH7730) || \
  25         defined(CONFIG_CPU_SUBTYPE_SH7786)
  26 #define CHCR_TS_LOW_MASK        0x00000018
  27 #define CHCR_TS_LOW_SHIFT       3
  28 #define CHCR_TS_HIGH_MASK       0x00300000
  29 #define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
  30 #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
  31         defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  32         defined(CONFIG_CPU_SUBTYPE_SH7780) || \
  33         defined(CONFIG_CPU_SUBTYPE_SH7785)
  34 #define CHCR_TS_LOW_MASK        0x00000018
  35 #define CHCR_TS_LOW_SHIFT       3
  36 #define CHCR_TS_HIGH_MASK       0x00100000
  37 #define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
  38 #endif
  39
  40 /* Transmit sizes and respective CHCR register values */
  41 enum {
  42         XMIT_SZ_8BIT            = 0,
  43         XMIT_SZ_16BIT           = 1,
  44         XMIT_SZ_32BIT           = 2,
  45         XMIT_SZ_64BIT           = 7,
  46         XMIT_SZ_128BIT          = 3,
  47         XMIT_SZ_256BIT          = 4,
  48         XMIT_SZ_128BIT_BLK      = 0xb,
  49         XMIT_SZ_256BIT_BLK      = 0xc,
  50 };
  51
  52 /* log2(size / 8) - used to calculate number of transfers */
  53 #define TS_SHIFT {                      \
  54         [XMIT_SZ_8BIT]          = 0,    \
  55         [XMIT_SZ_16BIT]         = 1,    \
  56         [XMIT_SZ_32BIT]         = 2,    \
  57         [XMIT_SZ_64BIT]         = 3,    \
  58         [XMIT_SZ_128BIT]        = 4,    \
  59         [XMIT_SZ_256BIT]        = 5,    \
  60         [XMIT_SZ_128BIT_BLK]    = 4,    \
  61         [XMIT_SZ_256BIT_BLK]    = 5,    \
  62 }
  63
  64 #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
  65                          (((i) & 0xc) << CHCR_TS_HIGH_SHIFT))
  66
  67 #else /* CONFIG_CPU_SH4A */
  68
  69 #define DMAOR_INIT      (0x8000 | DMAOR_DME)
  70
  71 #define CHCR_TS_LOW_MASK        0x70
  72 #define CHCR_TS_LOW_SHIFT       4
  73 #define CHCR_TS_HIGH_MASK       0
  74 #define CHCR_TS_HIGH_SHIFT      0
  75
  76 /* Transmit sizes and respective CHCR register values */
  77 enum {
  78         XMIT_SZ_8BIT    = 1,
  79         XMIT_SZ_16BIT   = 2,
  80         XMIT_SZ_32BIT   = 3,
  81         XMIT_SZ_64BIT   = 0,
  82         XMIT_SZ_256BIT  = 4,
  83 };
  84
  85 /* log2(size / 8) - used to calculate number of transfers */
  86 #define TS_SHIFT {                      \
  87         [XMIT_SZ_8BIT]          = 0,    \
  88         [XMIT_SZ_16BIT]         = 1,    \
  89         [XMIT_SZ_32BIT]         = 2,    \
  90         [XMIT_SZ_64BIT]         = 3,    \
  91         [XMIT_SZ_256BIT]        = 5,    \
  92 }
  93
  94 #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
  95
  96 #endif /* CONFIG_CPU_SH4A */
  97
  98 #endif