arch/sh/include/cpu-sh3/cpu/dma-register.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * SH3 CPU-specific DMA definitions, used by both DMA drivers
   4  *
   5  * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  */
   7 #ifndef CPU_DMA_REGISTER_H
   8 #define CPU_DMA_REGISTER_H
   9
  10 #define CHCR_TS_LOW_MASK        0x18
  11 #define CHCR_TS_LOW_SHIFT       3
  12 #define CHCR_TS_HIGH_MASK       0
  13 #define CHCR_TS_HIGH_SHIFT      0
  14
  15 #define DMAOR_INIT      DMAOR_DME
  16
  17 /*
  18  * The SuperH DMAC supports a number of transmit sizes, we list them here,
  19  * with their respective values as they appear in the CHCR registers.
  20  */
  21 enum {
  22         XMIT_SZ_8BIT,
  23         XMIT_SZ_16BIT,
  24         XMIT_SZ_32BIT,
  25         XMIT_SZ_128BIT,
  26 };
  27
  28 /* log2(size / 8) - used to calculate number of transfers */
  29 #define TS_SHIFT {                      \
  30         [XMIT_SZ_8BIT]          = 0,    \
  31         [XMIT_SZ_16BIT]         = 1,    \
  32         [XMIT_SZ_32BIT]         = 2,    \
  33         [XMIT_SZ_128BIT]        = 4,    \
  34 }
  35
  36 #define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
  37
  38 #endif